Low-overhead operating systems

• US 8,327,187 B1
• Filed: 09/20/2010
• Issued: 12/04/2012
• Est. Priority Date: 09/21/2009
• Status: Active Grant

• Current Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Original Assignee: Tilera Corporation (NVIDIA Corporation)
• Inventors: Metcalf, Christopher D.
• Primary Examiner(s): Ehne, Charles
• Application Number:
  US12/885,978
• Time in Patent Office: 806 Days
• Field of Search: 714/10, 714/47.1, 714/55
• US Class Current: 714/10
• CPC Class Codes: G06F 11/1482 by means of middleware or OS functionality
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0844 Multiple simultaneous or quasi-simultaneous cache accessing
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4221 : being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 15/16 : Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G06F 15/8023 : Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 21/79 : in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2212/452 : Instruction code
• CPC Class Codes: G06F 2212/502 : using adaptive policy
• CPC Class Codes: G06F 2212/601 : Reconfiguration of cache memory
• CPC Class Codes: G06F 2212/6032 : Way prediction in set-associative cache
• CPC Class Codes: G06F 2212/621 : Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 9/3004 : to perform operations on memory
• CPC Class Codes: G06F 9/4825 : Interrupt from clock, e.g. time of day
• CPC Class Codes: G06F 9/4881 : Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/5022 : Mechanisms to release resources
• CPC Class Codes: G06F 9/544 : Buffers; Shared memory; Pipes
• CPC Class Codes: H04L 45/08 : Learning-based routing, e.g. using neural networks or artificial intelligence
• CPC Class Codes: H04L 45/22 : Alternate routing
• CPC Class Codes: H04L 45/28 : using route fault recovery
• CPC Class Codes: H04L 47/83 : based on usage prediction
• CPC Class Codes: H04L 49/109 : Integrated on microchip, e.g. switch-on-chip

Abstract

Managing processes in a computing system comprising one or more cores includes receiving a request for a first process on a first core to execute with at least one predetermined task of an operating system disabled on the first core. In response to the request, the operating system determines whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core. The operating system grants the request or rejects the request in response to determining whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core.

Claims

1. A method for managing processes in a computing system comprising one or more cores, the method comprising:

receiving a request for a first process on a first core to execute with at least one predetermined task of an operating system disabled on the first core;

in response to the request, determining, by the operating system whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core; and

granting the request or rejecting the request in response to determining whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core.

2. The method of claim 1, further comprising isolating the first core from the other cores while the first process is executing if the request is granted.

3. The method of claim 1, wherein the predetermined task comprises regularly scheduled interrupts sent to a processor of the first core by the operating system.

4. The method of claim 3, wherein the regularly scheduled interrupts are based on a tinier.

5. The method of claim 1, wherein the predetermined task comprises sending interrupts to a processor of the first core to perform a predetermined function at the first core.

6. The method of claim 5, wherein the predetermined function comprises flushing a cache in the first core.

7. The method of claim 6, wherein the cache comprises a translation lookaside buffer storing translated addresses of data stored in memory coupled to the computing system.

8. The method of claim 6, wherein the cache comprises a data cache storing pages of data stored in memory coupled to the computing system.

9. The method of claim 8, wherein the interrupts to the processor of the first core are sent in response to a page stored in the data cache being allocated after having been freed.

10. The method of claim 1, wherein determining whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core comprises:

determining whether any conditions exist that are associated with the one or more potential errors.

11. The method of claim 10, wherein determining whether any conditions exist that are associated with the one or more potential errors includes determining whether any other processes would be executing concurrently with the first process on the first core.

12. The method of claim 10, wherein determining whether any conditions exist that are associated with the one or more potential errors includes determining whether the first process is associated with a user-space or a kernel-space, and the request is granted in response to determining that the first process would not be executing concurrently with any other processes on the first core and that the first process is associated with a user-space and not a kernel-space.

13. The method of claim 1, further comprising, in response to granting the request, disabling the predetermined task of the operating system on the first core.

14. The method of claim 13, wherein disabling the predetermined task of the operating system on the first core comprises writing a predetermined value in a resister in the first core.

15. The method of claim 13, further comprising, after the first core finishes executing the first process, enabling the predetermined task of the operating system on the first core.

16. The method of claim 15, further comprising storing a request to perform the predetermined task received while the predetermined task is disabled, and performing the predetermined task after enabling the predetermined task of the operating system on the first core.

17. The method of claim 16, wherein the predetermined task comprises sending an interrupt to a processor of the first core to flush a cache in the first core.

18. The method of claim 15, wherein the first core finishes executing the first process in response to an event that is handled by a second process executing on the first core.

19. The method of claim 1, wherein the request comprises a value of a parameter accessible to the operating system.

20. The method of claim 19, wherein the parameter comprises a command-line parameter of a program executing on the computing system, or a parameter whose value is programmed into a program executing on the computing system or programmed into a script used to initiate execution of a program executing on the computing system.

21. A computer program product tangibly embodied on a computer-readable storage device, the computer program product for managing processes in a computing system comprising one or more cores, the computer program including instructions for causing the computing system to:

receive a request for a first process on a first core to execute with at least one predetermined task of an operating system disabled on the first core;

in response to the request, determine, by the operating system whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core; and

grant the request or reject the request in response to determining whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core.

22. The computer program product of claim 21, wherein the computer program further comprises instructions to isolate the first core from the other cores while the first process is executing if the request is granted.

23. The computer program product of claim 22, wherein the predetermined task comprises sending interrupts to a processor of the first core to perform a predetermined function at the first core.

24. The computer program product of claim 23, wherein the predetermined function comprises flushing a cache in the first core.

25. The computer program product of claim 24, wherein the cache comprises a translation lookaside buffer storing translated addresses of data stored in memory coupled to the computing system.

26. The computer program product of claim 21, wherein the predetermined task comprises regularly scheduled interrupts sent to a processor of the first core by the operating system.

27. The computer program product of claim 26, wherein the regularly scheduled interrupts are based on a timer.

28. The computer program product of claim 21, wherein instructions to determine whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core comprises instructions to:

determine whether any conditions exist that are associated with the one or more potential errors.

29. The computer program product of claim 28, wherein instructions to determine whether any conditions exist that are associated with the one or more potential errors includes instructions to

determine whether any other processes would be executing concurrently with the first process on the first core.

30. The computer program product of claim 28, wherein instructions to determine whether any conditions exist that are associated with the one or more potential errors includes instructions to

determine whether the first process is associated with a user-space or a kernel-space, and the request is granted in response to determining that the first process would not be executing concurrently with any other processes on the first core and that the first process is associated with a user-space and not a kernel-space.

31. The computer program product of claim 28, wherein the computer program further comprises instructions to disable the predetermined task of the operating system on the first core, in response to granting the request.

32. The computer program product of claim 31, wherein the computer program further comprises instructions to

store a request to perform the predetermined task received while the predetermined task is disabled, and

perform the predetermined task after enabling the predetermined task of the operating system on the first core.

33. A computing system, comprising:

one or more cores configured to run an operating system;

a timer accessible to one or more of the cores configured to be enabled and disabled according to information stored in a register; and

processors of one or more of the cores configured to;

receive a request for a first process on a first core to execute with at least one predetermined task of the operating system associated with the timer disabled on the first core;

in response to the request, determine, by the operating system whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core; and

grant the request or rejecting the request in response to determining whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core.

34. The system of claim 33, wherein the processors of one or more of the cores are further configured to isolate the first core from the other cores while the first process is executing if the request is granted.

35. The system of claim 33, wherein the predetermined task comprises regularly scheduled interrupts sent to a processor of the first core by the operating system.

36. The system of claim 35, wherein the regularly scheduled interrupts are based on a timer.

37. The system of claim 35, wherein the predetermined task comprises sending interrupts to a processor of the first core to perform a predetermined function at the first core.

38. The system of claim 37, wherein the predetermined function comprises flushing a cache in the first core.

39. The system of claim 37, wherein the cache comprises a translation lookaside buffer storing translated addresses of data stored in memory coupled to the computing system.

40. The system of claim 33, further configured to:

determine whether any conditions exist that are associated with the one or more potential errors.

41. The system of claim 40, further configured to:

determine whether any other processes would be executing concurrently with the first process on the first core.

42. The system of claim 40, further configured to:

determine whether the first process is associated with a user-space or a kernel-space, and the request is granted in response to determining that the first process would not be executing concurrently with any other processes on the first core and that the first process is associated with a user-space and not a kernel-space.

43. The system of claim 40, further configured to:

disable the predetermined task of the operating system on the first core, in response to granting the request.

44. The system of claim 43, further configured to:

store a request to perform the predetermined task received while the predetermined task is disabled, and

perform the predetermined task after enabling the predetermined task of the operating system on the first core.