High-speed transceiver tester incorporating jitter injection
First Claim
Patent Images
1. A high-speed digital tester, comprising:
- a jitter generator that includes;
a multiplexer configured to receive a first clock input signal and a second clock input signal phased-shifted relative to said first clock input signal by a delay, said multiplexer having a multiplexer output and a multiplexer select port;
a phase filter operatively connected to said multiplexer output; and
a phase selection signal generator in operative communication with said multiplexer select port and configured to generate a phase-selecting signal for continually selecting between said first clock signal and said second clock signal so as to generate a modulated signal containing a high-frequency component;
wherein said phase filter is designed and configured to remove said high-frequency component of said modulated signal.
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Abstract
A tester for testing high-speed serial transceiver circuitry. The tester includes a jitter generator that uses a rapidly varying phase-selecting signal to select between two or more differently phased clock signals to generate a phase-modulated signal. The phase-selecting signal is designed to contain low- and high-frequency components. The phase-modulated signal is input into a phase filter to filter unwanted high-frequency components. The filtered output of the phase filter is input into a data-transmit serializer to serialize a low-speed parallel word into a high-speed jittered test pattern for input into the transceiver circuitry.
91 Citations
26 Claims
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1. A high-speed digital tester, comprising:
a jitter generator that includes; a multiplexer configured to receive a first clock input signal and a second clock input signal phased-shifted relative to said first clock input signal by a delay, said multiplexer having a multiplexer output and a multiplexer select port; a phase filter operatively connected to said multiplexer output; and a phase selection signal generator in operative communication with said multiplexer select port and configured to generate a phase-selecting signal for continually selecting between said first clock signal and said second clock signal so as to generate a modulated signal containing a high-frequency component; wherein said phase filter is designed and configured to remove said high-frequency component of said modulated signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of generating a high-speed jittered test pattern, comprising:
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generating a rapidly varying phase signal containing a low-frequency phase signal and at least one high-frequency component by continually selecting between two or more differently phased clock signals; filtering said rapidly varying phase signal so as to create a filtered phase signal substantially lacking said at least one high-frequency component; and serializing parallel data as a function of said filtered phase signal so as to create a high-speed jittered test pattern. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A method of testing a device under test having a serial receive port and a serial transmit port, comprising:
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generating a rapidly varying phase signal containing a low-frequency phase signal and at least one high-frequency component by continually selecting between two or more differently phased clock signals; filtering said rapidly varying phase signal so as to create a filtered phase signal substantially lacking said at least one high-frequency component; serializing parallel data on a plurality of data input ports as a function of said filtered phase signal so as to create a serial test pattern; inputting said serial test pattern into the serial receive port of the device under test; receiving a serial data signal from the serial transmit port of the device under test; deserializing said serial data signal into parallel data so as to create a deserialized data signal; and reserializing said deserialized data signal for input into the serial receive port of the device under test. - View Dependent Claims (24, 25)
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26. A method of testing a device under test having a serial receive port and a serial transmit port, comprising:
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enabling the device under test to transmit a serial data signal on its serial transmit port; receiving said serial data signal from the serial transmit port of the device under test; deserializing said serial data signal into parallel data; inputting said parallel data into a plurality of data input ports of a serializer; generating a rapidly varying phase signal containing a low-frequency phase signal and at least one high-frequency component by continually selecting between two or more differently phased clock signals; filtering said rapidly varying phase signal so as to create a filtered phase signal substantially lacking said at least one high-frequency component; serializing data on said plurality of data input ports as a function of said filtered phase signal so as to create a serial test signal; inputting said serial test signal into the serial receive port of the device under test; and enabling the device under test to compare the received signal against said serial data signal.
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Specification