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Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein

  • US 8,329,538 B2
  • Filed: 04/08/2011
  • Issued: 12/11/2012
  • Est. Priority Date: 07/09/2008
  • Status: Active Grant
First Claim
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1. A method for forming a shielded gate trench field effect transistor (FET), the method comprising:

  • forming a trench in a semiconductor region;

    forming a shield electrode on a bottom surface of the trench;

    forming an inter-electrode dielectric (IED) on an exposed surface of the shield electrode, the IED including a low-k dielectric;

    forming a gate dielectric lining at least one of a sidewall of the trench and an exposed surface of the IED;

    forming a conductive liner layer on an exposed surface of the gate dielectric; and

    forming a gate electrode on an exposed surface of the conductive liner layer.

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