Devices, methods, and systems with MOS-gated trench-to-trench lateral current flow

• US 8,330,217 B2
• Filed: 04/07/2010
• Issued: 12/11/2012
• Est. Priority Date: 09/08/2006
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Blanchard, Richard A.
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US12/755,658
• Publication Number:
  US 20100194467A1
• Time in Patent Office: 979 Days
• Field of Search: 257335-336, 257/E29.256, 257/E21.418
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A DMOS transistor is fabricated with its source/body/deep body regions formed on the walls of a first set of trenches, and its drain regions formed on the walls of a different set of trenches. A gate region that is formed in a yet another set of trenches can be biased to allow carriers to flow from the source to the drain. Lateral current low from source/body regions on trench walls increases the active channel perimeter to a value well above the amount that would be present if the device was fabricated on just the surface of the wafer. Masking is avoided while open trenches are present. A transistor with a very low on-resistance per unit area is obtained.

Claims

1. A system comprising:

a power source having limited voltage, power, and/or energy;

a load element, which is operatively connected to said power source through at least one electronic switch;

wherein said switch comprises a three-dimensional active device structure, comprising;

a downwardly extended source diffusion having a first conductivity type;

a downwardly extended body diffusion having a second conductivity type, and laterally positioned adjacent to said source diffusion;

a downwardly extended deep body diffusion having a second conductivity type, and laterally adjoining said body diffusion;

a downwardly extended gate electrode, laterally positioned in proximity to at least part of said body diffusion and insulated therefrom; and

a downwardly extended drain, positioned so that said body diffusion is laterally interposed between said drain and said source;

wherein said source, body, deep body, gate and drain jointly define a respective DMOS-type device structure, at each of multiple different horizontal planes.

2. The system of claim 1, further comprising a conductor which electrically contacts said drain.

3. The system of claim 1, further comprising a vertical-walled downwardly-extending trench, filled with a doped semiconductor material, which electrically contacts said drain.

4. The system of claim 1, wherein said diffusions consist of essentially a dopant in silicon.

5. The system of claim 1, wherein said first conductivity is N-type.

6. The system of claim 1, wherein said source and body diffusions are both laterally outdiffused from a single trench;

and said deep-body diffusion does not correspond solely to outdiffusion from said single trench.

7. The system of claim 1, wherein said gate electrode is laterally surrounded by insulator.

8. A system comprising:

a power source having limited voltage, power, and/or energy; and

a load element, which is operatively connected to said power source through at least one electronic switch;

wherein said switch comprises a downwardly extended lateral-conduction device structure, comprising;

a merged source/body trench, and source and deep body diffusions of opposite conductivity types adjacent to the walls thereof;

wherein said trench is narrowed at locations where said source diffusions are present;

a source contact conductor which extends into said merged trench, and makes contact with said source and deep body diffusions;

a gate trench, containing conductive material which is capacitively coupled to said body diffusion; and

a downwardly extended drain diffusion, laterally spaced to receive charge carriers from said source diffusion under at least some conditions.

9. The system of claim 8, further comprising a conductor which electrically contacts said drain diffusion.

10. The system of claim 8, further comprising a vertical-walled downwardly-extending trench, filled with a doped semiconductor material, which electrically contacts said drain diffusion.

11. The system of claim 8, wherein said source/body trench has vertical sidewalls.

12. The system of claim 8, wherein said source/body trench has notches, in the sidewalls thereof, wherever said source diffusion is not present.

13. The system of claim 8, wherein said diffusions comprise silicon plus a dopant.

14. The system of claim 8, wherein said source diffusion is N-type.

15. The system of claim 8, wherein said source diffusion is laterally surrounded by a second-type body diffusion outdiffused from substantially the same source locations as said source diffusion.

16. The system of claim 8, wherein said conductive material in said gate trench is laterally surrounded by insulator.