Semiconductor device

• US 8,330,233 B2
• Filed: 07/15/2010
• Issued: 12/11/2012
• Est. Priority Date: 07/24/2009
• Status: Active Grant

• Current Assignee: Sanken Electric Company Limited
• Original Assignee: Sanken Electric Company Limited
• Inventors: Omori, Tomoyuki
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US12/836,911
• Publication Number:
  US 20110018101A1
• Time in Patent Office: 880 Days
• Field of Search: 257/409, 257/491, 257/492, 257/548, 257/E29.012, 257/E29.019
• US Class Current: 257/409
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device 1 including a cell region 2 formed with a semiconductor element 6 and a periphery region 3 formed in the periphery of the cell region 2. The semiconductor region 1 is arranged with an n⁻ type drift region 12 formed in the cell region 2 and periphery region 3, a plurality of p⁻ type columnar regions formed in the n⁻ drift region 12 of the cell region 2, a plurality of p⁻ type columnar resistance improvement regions 23n formed in the n⁻ type drift region 12 of the periphery region 3, and a plurality of electrical field buffer regions 24n formed in an upper part of the p⁻ type columnar region 23n. An interval Sn between the electrical field buffer region 24n and an adjacent electrical field buffer region 24n is different between an interior side and an exterior side of the periphery region 3.

Claims

1. A semiconductor device comprising:

a cell region formed with semiconductor elements;

a periphery region formed on a periphery of the cell region;

a first conduction type region of a first conductive type formed in the cell region and the periphery region;

a plurality of first columnar regions of a second conductive type formed in the first conduction type region of the cell region;

a plurality of second columnar regions of the second conductive type formed in the first conduction type region of the periphery region; and

a plurality of electrical field buffer regions of the second conductive type formed on an upper part of each of the second columnar regions,

wherein an interval between one of the electrical field buffer regions and an adjacent of one electrical field buffer regions is different between an interior side and an exterior side of the periphery region, and a distance between centers of one of the first columnar regions and an adjacent one of the first columnar regions, a distance between centers of one of the second columnar regions and an adjacent one of the second columnar regions, and a width of the first and the second columnar regions are equal.

2. The semiconductor device according to claim 1, wherein the interval between the one of the electrical field buffer regions and the adjacent one of the electrical field buffer regions on the interior side of the periphery region is smaller than the interval between the one of the electrical field buffer regions and the adjacent one of the electrical field buffer regions on the exterior side of the periphery region.

3. The semiconductor device according to claim 2, wherein the interval between the one of the electrical field buffer regions and the adjacent one of the electrical field buffer regions becomes gradually larger from the interior side of the periphery region approaching the exterior side.

4. The semiconductor device according to claim 3, wherein a width of the electrical field buffer regions becomes gradually smaller from the interior side of the periphery region approaching the exterior side.

5. The semiconductor device according to claim 3, wherein a depth of the electrical field buffer regions becomes gradually shallower approaching the exterior side of the periphery region.

6. The semiconductor device according to claim 2, wherein a width of the electrical field buffer regions becomes gradually smaller from the interior side of the periphery region approaching the exterior side.

7. The semiconductor device according to claim 6, wherein a depth of the electrical field buffer regions becomes gradually shallower approaching the exterior side of the periphery region.

8. The semiconductor device according to claim 2, wherein a depth of the electrical field buffer regions becomes gradually shallower approaching the exterior side of the periphery region.