Universal inter-layer interconnect for multi-layer semiconductor stacks
First Claim
1. A circuit arrangement, comprising:
- a plurality of semiconductor dies physically and electrically coupled to one another in a stack, each semiconductor die including opposing faces, wherein at least one face of each semiconductor die includes circuit logic integrated thereon and defining a circuit layer that includes at least one functional unit, wherein at least one face of each semiconductor die includes an inter-layer interface region disposed thereon, and wherein each inter-layer interface region on each semiconductor die is disposed at substantially the same topographic location when the respective semiconductor die is disposed within the stack; and
an inter-layer bus electrically coupling the functional units on the plurality of semiconductor dies to one another, the inter-layer bus comprising a plurality of electrical conductors disposed within the inter-layer interface region of each semiconductor die and extending between the opposing faces of each semiconductor die, wherein respective electrical conductors disposed in the inter-layer interface regions of adjacent semiconductor dies in the stack are electrically coupled to one another when the plurality of circuit layers are physically and electrically coupled to one another in the stack;
wherein each semiconductor die includes a regular array of contact pads disposed on at least one face of such semiconductor die, wherein the plurality of electrical conductors disposed within the inter-layer interface region of such semiconductor die and extending between the opposing faces of each semiconductor die are topographically aligned and electrically coupled to at least a first subset of the regular array of contact pads that are topographically disposed within the inter-layer interface region of such semiconductor die, wherein at least a second subset of the regular array of contact pads that are disposed outside of the inter-layer interface region of such semiconductor die define a power distribution network for the circuit layer on such semiconductor die, wherein a contact pad pitch for the contact pads electrically coupled to the inter-layer bus is greater than that for the contact pads electrically coupled to the power distribution network, and wherein at least a third subset of the regular array of contact pads that are disposed outside of the inter-layer interface region of such semiconductor die are dummy contact pads.
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Accused Products
Abstract
A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack.
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Citations
22 Claims
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1. A circuit arrangement, comprising:
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a plurality of semiconductor dies physically and electrically coupled to one another in a stack, each semiconductor die including opposing faces, wherein at least one face of each semiconductor die includes circuit logic integrated thereon and defining a circuit layer that includes at least one functional unit, wherein at least one face of each semiconductor die includes an inter-layer interface region disposed thereon, and wherein each inter-layer interface region on each semiconductor die is disposed at substantially the same topographic location when the respective semiconductor die is disposed within the stack; and an inter-layer bus electrically coupling the functional units on the plurality of semiconductor dies to one another, the inter-layer bus comprising a plurality of electrical conductors disposed within the inter-layer interface region of each semiconductor die and extending between the opposing faces of each semiconductor die, wherein respective electrical conductors disposed in the inter-layer interface regions of adjacent semiconductor dies in the stack are electrically coupled to one another when the plurality of circuit layers are physically and electrically coupled to one another in the stack; wherein each semiconductor die includes a regular array of contact pads disposed on at least one face of such semiconductor die, wherein the plurality of electrical conductors disposed within the inter-layer interface region of such semiconductor die and extending between the opposing faces of each semiconductor die are topographically aligned and electrically coupled to at least a first subset of the regular array of contact pads that are topographically disposed within the inter-layer interface region of such semiconductor die, wherein at least a second subset of the regular array of contact pads that are disposed outside of the inter-layer interface region of such semiconductor die define a power distribution network for the circuit layer on such semiconductor die, wherein a contact pad pitch for the contact pads electrically coupled to the inter-layer bus is greater than that for the contact pads electrically coupled to the power distribution network, and wherein at least a third subset of the regular array of contact pads that are disposed outside of the inter-layer interface region of such semiconductor die are dummy contact pads. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 18, 19, 20)
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15. A circuit arrangement, comprising:
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a plurality of semiconductor dies physically and electrically coupled to one another in a stack, each semiconductor die including opposing faces, wherein at least one face of each semiconductor die includes circuit logic integrated thereon and defining a circuit layer that includes at least one functional unit, wherein at least one face of each semiconductor die includes an inter-layer interface region disposed thereon, and wherein each inter-layer interface region on each semiconductor die is disposed at substantially the same topographic location when the respective semiconductor die is disposed within the stack; a first inter-layer bus electrically coupling the functional units on the plurality of semiconductor dies to one another, the first inter-layer bus comprising a plurality of electrical conductors disposed within the inter-layer interface region of each semiconductor die and extending between the opposing faces of each semiconductor die, wherein respective electrical conductors disposed in the first inter-layer interface regions of adjacent semiconductor dies in the stack are electrically coupled to one another when the plurality of circuit layers are physically and electrically coupled to one another in the stack; and a second inter-layer bus topographically separated from the first inter-layer bus, wherein the stack of semiconductor dies defines first and second vertically-oriented supernodes, wherein the circuit layers on multiple semiconductor dies in the stack include functional units allocated to each of the first and second supernodes, with the functional units allocated to the first supernode coupled to the first inter-layer bus and the functional units allocated to the second supernode coupled to the second inter-layer bus. - View Dependent Claims (16, 17)
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21. A circuit arrangement, comprising:
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a semiconductor stack including a plurality of circuit layers upon which is defined circuit logic, the semiconductor stack comprising a plurality of semiconductor dies physically and electrically coupled to one another, each semiconductor die including opposing faces, wherein at least one face of each semiconductor die includes circuit logic integrated thereon that includes at least one functional unit and that defines a circuit layer from among the plurality of circuit layers; a plurality of independently operating vertically-oriented supernodes defined by the circuit logic and disposed on multiple circuit layers of the semiconductor stack, each vertically-oriented supernode including a plurality of functional units distributed vertically among at least a subset of the plurality of circuit layers; a plurality of inter-layer buses, each inter-layer bus dedicated to one of the vertically-oriented supernodes and electrically coupling together the functional units thereof, each inter-layer bus comprising a plurality of electrical conductors disposed within a corresponding inter-layer interface region disposed on each semiconductor die and extending between the opposing faces of each semiconductor die, wherein respective electrical conductors disposed in the inter-layer interface regions of adjacent semiconductor dies in the stack are electrically coupled to one another when the plurality of circuit layers are physically and electrically coupled to one another in the stack, and wherein for each vertically-oriented supernode, the inter-layer interface regions therefor are disposed at substantially the same topographic location when their respective semiconductor dies are disposed within the stack; and an inter-layer bus disposed in one of the plurality of circuit layers and configured to communicate data between the plurality of vertically-oriented supernodes. - View Dependent Claims (22)
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Specification