Dual mode rail-to-rail buffer for low voltage memory
First Claim
1. A system for voltage buffering within an integrated circuit (IC), the system comprising:
- a first buffer comprising an input and an output, wherein the first buffer is configured to buffer a received maximum input voltage approximately equal to a positive voltage supply powering the system;
a second buffer comprising an input and an output, wherein the input of the first buffer is coupled to the input of the second buffer, wherein the output of the first buffer is coupled to the output of the second buffer, and wherein the second buffer is configured to buffer a received minimum input voltage approximately equal to a negative voltage supply powering the system;
a controller configured to selectively enable only the first buffer or the second buffer at any given time;
a bias generator configured to generate a first bias voltage and a second bias voltage;
a first switch configured to enable the first buffer by selectively coupling the first bias voltage to the first buffer responsive to a first control signal from the controller; and
a second switch configured to enable the second buffer by selectively coupling the second bias voltage to the second buffer responsive to a second control signal from the controller.
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Accused Products
Abstract
A system for voltage buffering within an integrated circuit (IC). The system can include a first buffer having an input and an output. The first buffer can be configured to buffer a received maximum input voltage approximately equal to a positive voltage supply powering the system. The system can include a second buffer having an input and an output. The input of the first buffer can be coupled to the input of the second buffer. The output of the first buffer can be coupled to the output of the second buffer. The second buffer can be configured to buffer a received minimum input voltage approximately equal to a negative voltage supply powering the system. The system further can include a controller configured to selectively enable only the first buffer or the second buffer at any given time.
15 Citations
16 Claims
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1. A system for voltage buffering within an integrated circuit (IC), the system comprising:
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a first buffer comprising an input and an output, wherein the first buffer is configured to buffer a received maximum input voltage approximately equal to a positive voltage supply powering the system; a second buffer comprising an input and an output, wherein the input of the first buffer is coupled to the input of the second buffer, wherein the output of the first buffer is coupled to the output of the second buffer, and wherein the second buffer is configured to buffer a received minimum input voltage approximately equal to a negative voltage supply powering the system; a controller configured to selectively enable only the first buffer or the second buffer at any given time; a bias generator configured to generate a first bias voltage and a second bias voltage; a first switch configured to enable the first buffer by selectively coupling the first bias voltage to the first buffer responsive to a first control signal from the controller; and a second switch configured to enable the second buffer by selectively coupling the second bias voltage to the second buffer responsive to a second control signal from the controller. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A circuit for voltage buffering in a complementary metal oxide semiconductor (CMOS) integrated circuit (IC), the circuit comprising:
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a rail-to-rail buffer comprising; an N-type metal oxide semiconductor (NMOS) buffer comprising an NMOS input and an output, wherein the NMOS buffer is configured to buffer a received maximum input voltage approximately equal to a positive voltage supply powering the circuit, and a P-type metal oxide semiconductor (PMOS) buffer comprising a PMOS input and an output, wherein the NMOS input of the NMOS buffer is coupled to the PMOS input of the PMOS buffer, wherein the output of the NMOS buffer is coupled to the output of the PMOS buffer, and wherein the PMOS buffer is configured to buffer a received minimum input voltage approximately equal to a negative voltage supply powering the circuit; a controller configured to selectively enable only the NMOS buffer or the PMOS buffer at any given time; a bias generator configured to generate a first bias voltage and a second bias voltage; a first switch configured to enable the NMOS buffer by selectively coupling the first bias voltage to the NMOS buffer responsive to a first control signal from the controller; and a second switch configured to enable the PMOS buffer by selectively coupling the second bias voltage to the PMOS buffer responsive to a second control signal from the controller. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method of voltage buffering within an integrated circuit (IC), the method comprising:
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determining whether a voltage of a received mode signal is within one of two different voltage ranges; responsive to determining that the voltage is in the first voltage range, enabling a first buffer while concurrently disabling a second buffer; and responsive to determining that the voltage is in the second voltage range, enabling the second buffer while concurrently disabling the first buffer, wherein the first and the second buffers receive the mode signal as a common input signal and generate a common output signal; and wherein enabling the first buffer while concurrently disabling the second buffer comprises; coupling a first bias voltage to a current source biasing the first buffer; and decoupling a second bias voltage from a current source biasing the second buffer. - View Dependent Claims (15, 16)
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Specification