Inverting zipper repeater circuit

• US 8,330,515 B2
• Filed: 06/24/2011
• Issued: 12/11/2012
• Est. Priority Date: 06/15/2004
• Status: Active Grant

• Current Assignee: Robert P. Masleid
• Original Assignee: Robert P. Masleid
• Inventors: Masleid, Robert P
• Primary Examiner(s): Hiltunen, Thomas J
• Application Number:
  US13/168,894
• Publication Number:
  US 20120161839A1
• Time in Patent Office: 536 Days
• Field of Search: 327/170, 327/227, 327/375, 327/376
• US Class Current: 327/170
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 5/12 by steepening leading or trailing edges

Abstract

Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described.

Claims

1. A circuit comprising:

a chain of inverters operable to produce a first delayed version of an input signal and a second delayed version of the input signal;

a first subcircuit configured to receive the first delayed version of the input signal and coupled to an output terminal;

a second subcircuit comprising a first pulse generator operable to generate a rising output transition at the output terminal responsive to a falling transition of the input signal, wherein the first pulse generator is further operable to access the input signal and the second delayed version of the input signal; and

a third subcircuit comprising a second pulse generator operable to generate a falling output transition at the output terminal responsive to a rising transition of the input signal, wherein the second pulse generator is further operable to access the input signal and the second delayed version of the input signal.

2. The circuit of claim 1, further comprising a first latching circuit coupled to an output node of the first pulse generator and to the output terminal.

3. The circuit of claim 2, further comprising a second latching circuit coupled to an output node of the second pulse generator and to the output terminal.

4. The circuit of claim 1, wherein the second subcircuit is further operable to generate a rising edge at the output terminal responsive to a falling edge of the input signal while maintaining a rising edge advantage over the falling edge.

5. The circuit of claim 1, wherein the third subcircuit is further operable to generate a falling edge at the output terminal responsive to a rising edge of the input signal while maintaining a falling edge advantage over the rising edge.

6. The circuit of claim 1, wherein the first subcircuit comprises:

a first inverter operable to receive the first delayed version of the input signal; and

a second inverter, wherein the first inverter is coupled in series with the second inverter and the output terminal,

wherein the first subcircuit is further operable to maintain a state of the output terminal.

7. The circuit of claim 1, wherein the first pulse generator is further operable to generate a first pulse signal that activates a first output transistor operable to generate the rising output transition at the output terminal, and wherein the second pulse generator is further operable to generate a second pulse signal that activates a second output transistor operable to generate the falling output transition at the output terminal.

8. A repeater circuit comprising:

a first subcircuit configured to receive an input signal and coupled to an output terminal;

a chain of inverters configured to receive the input signal and configured to output a signal;

a first pulse generator coupled to the chain of inverters and configured to receive the input signal and to receive the signal, wherein the first pulse generator is operable to generate a rising output transition at the output terminal responsive to a falling transition of the input signal;

a first latching circuit coupled to an output node of the first pulse generator and to the output terminal;

a second pulse generator coupled to the chain of inverters and configured to receive the input signal and to receive the signal, wherein the second pulse generator is operable to generate a falling output transition at the output terminal responsive to a rising transition of the input signal; and

a second latching circuit coupled to an output node of the second pulse generator and to the output terminal.

9. The repeater circuit of claim 8, wherein the first pulse generator is responsive to a falling edge of the input signal.

10. The repeater circuit of claim 8, wherein the second pulse generator is responsive to a rising edge of the input signal.

11. The repeater circuit of claim 8, wherein the first pulse generator further comprises:

a NOR gate including an output node and a plurality of input nodes configured to receive the signal from the chain of inverters and the input signal; and

an NFET coupled to the output node of the NOR gate, wherein the NFET is coupled to the first latching circuit and is coupled to a first output transistor.

12. The repeater circuit of claim 11, wherein the first latching circuit comprises:

a precharge circuit coupled to the output node of the first pulse generator; and

a half latch circuit coupled to the first output transistor.

13. The repeater circuit of claim 8, wherein the second pulse generator further comprises:

a NAND gate including an output node and a plurality of input nodes configured to receive the signal from the chain of inverters and the input signal; and

a PFET coupled to the output node of the NAND gate, wherein the PFET is coupled to the second latching circuit and is coupled to a second output transistor.

14. The repeater circuit of claim 13, wherein the second latching circuit comprises:

a precharge circuit coupled to the output node of the second pulse generator; and

a half latch circuit coupled to the second output transistor.

15. A circuit comprising:

means for generating a first delayed version of an input signal and a second delayed version of the input signal;

means for receiving the first delayed version of the input signal, wherein the means for receiving is coupled to an output terminal;

means for generating a rising output transition at the output terminal responsive to a falling transition of the input signal, wherein the means for generating the rising output transition is further operable to access the input signal and the second delayed version of the input signal; and

means for generating a falling output transition at the output terminal responsive to a rising transition of the input signal, wherein the means for generating the falling output transition is further operable to access the input signal and the second delayed version of the input signal.

16. The circuit of claim 15, wherein the means for generating the rising output transition is further operable to generate a rising edge at the output terminal responsive to a falling edge of the input signal while maintaining a rising edge advantage over the falling edge.

17. The circuit of claim 15, wherein the means for generating the falling output transition is further operable to generate a falling edge at the output terminal responsive to a rising edge of the input signal while maintaining a falling edge advantage over the rising edge.

18. The circuit of claim 15, wherein the means for receiving the first delayed version of the input signal comprises:

first means for receiving and inverting the first delayed version of the input signal; and

second means for receiving and inverting, wherein the first means for receiving and inverting is coupled in series with the second means for receiving and inverting and the output terminal,

wherein the means for receiving the first delayed version of the input signal is further operable to maintain a state of the output terminal.

19. The circuit of claim 15, wherein the means for generating the rising output transition comprises means for generating a first pulse signal that activates a first output transistor operable to generate the rising output transition at the output terminal, and wherein the means for generating the falling output transition comprises means for generating a second pulse signal that activates a second output transistor operable to generate the falling output transition at the output terminal.

20. The circuit of claim 15, further comprising:

first means for latching coupled to an output node of the means for generating the rising output transition and coupled to the output terminal; and

second means for latching coupled to an output node of the means for generating the falling output transition and coupled to the output terminal.