Integrated SRAM and FLOTOX EEPROM memory device
First Claim
1. An integrated nonvolatile static random access memory circuit formed on a substrate, the integrated nonvolatile static random access memory circuit comprising:
- a static random access memory cell connected to receive and retain a digital signal indicative of a data bit at a first bit line and a complementary digital signal indicative of a complementary data bit a second bit line and in communication with an SRAM word line for controlling access to the first and second bit lines; and
a first EEPROM element in communication with the static random access memory cell to receive and permanently retain the digital signal from the static random access memory cell;
wherein the first EEPROM element comprises;
a first floating gate tunnel oxide transistor comprising an EEPROM control gate connected to an EEPROM word line for controlling activation of the first floating gate tunnel oxide transistor and a floating gate placed over a channel region between a drain and source of the first floating gate tunnel oxide transistor for permanently retaining the digital signal and placed over an insulating layer wherein the insulating layer has a first tunnel window placed in proximity to the source of the first floating gate tunnel oxide transistor for providing a path for transfer of charge between the floating gate and the source during erasing to set an erased threshold voltage level of the first floating gate tunnel oxide transistor and providing a path for transfer of charge between the floating gate and the channel for programming to set a programmed threshold voltage level of the first floating gate tunnel oxide transistor,a first select gating transistor having a drain connected to the static random access memory cell, a source connected to the drain of the floating gate tunnel oxide transistor, and a gate connected to a first select gating signal for controlling access between the floating gate tunnel oxide transistor and the static random access memory cell, anda second select gating transistor having a drain connected to the source of the floating gate tunnel oxide transistor, a source connected to a source line, and a control gate connected to a second select gating signal for controlling access between the floating gate tunnel oxide transistor and the source line.
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Accused Products
Abstract
A nonvolatile SRAM circuit has an SRAM cell and one or two FLOTOX EEPROM cells connected to the data storage terminals of the SRAM cell. In programming to a first data level, the threshold voltage of a FLOTOX EEPROM transistor is brought to a programmed voltage level greater than a read voltage level and erasing to a second data level, the threshold voltage of the FLOTOX EEPROM transistor is brought to an erased voltage level less than the read voltage level. The nonvolatile SRAM array provides for restoring data to an SRAM cell from a FLOTOX EEPROM memory cell(s) at a power initiation and storing data to the FLOTOX EEPROM memory cell(s) to the SRAM cell at power termination. A power detection circuit for providing signals indicating power initiation and power termination to instigate restoration and storing of data between an SRAM cell and a FLOTOX EEPROM cell(s).
31 Citations
90 Claims
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1. An integrated nonvolatile static random access memory circuit formed on a substrate, the integrated nonvolatile static random access memory circuit comprising:
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a static random access memory cell connected to receive and retain a digital signal indicative of a data bit at a first bit line and a complementary digital signal indicative of a complementary data bit a second bit line and in communication with an SRAM word line for controlling access to the first and second bit lines; and a first EEPROM element in communication with the static random access memory cell to receive and permanently retain the digital signal from the static random access memory cell; wherein the first EEPROM element comprises; a first floating gate tunnel oxide transistor comprising an EEPROM control gate connected to an EEPROM word line for controlling activation of the first floating gate tunnel oxide transistor and a floating gate placed over a channel region between a drain and source of the first floating gate tunnel oxide transistor for permanently retaining the digital signal and placed over an insulating layer wherein the insulating layer has a first tunnel window placed in proximity to the source of the first floating gate tunnel oxide transistor for providing a path for transfer of charge between the floating gate and the source during erasing to set an erased threshold voltage level of the first floating gate tunnel oxide transistor and providing a path for transfer of charge between the floating gate and the channel for programming to set a programmed threshold voltage level of the first floating gate tunnel oxide transistor, a first select gating transistor having a drain connected to the static random access memory cell, a source connected to the drain of the floating gate tunnel oxide transistor, and a gate connected to a first select gating signal for controlling access between the floating gate tunnel oxide transistor and the static random access memory cell, and a second select gating transistor having a drain connected to the source of the floating gate tunnel oxide transistor, a source connected to a source line, and a control gate connected to a second select gating signal for controlling access between the floating gate tunnel oxide transistor and the source line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A nonvolatile static random access memory array comprising:
a plurality of integrated nonvolatile static random access memory circuits arranged in an array of rows and columns, each of the integrated nonvolatile static random access memory circuits comprising; a static random access memory cell connected to receive and retain a digital signal indicative of a data bit at a first bit line of a plurality of bit lines and a complementary digital signal indicative of a complementary data bit a second bit line of the plurality of bit lines and in communication with an SRAM word line for controlling access to the first and second bit lines; and a first EEPROM element in communication with the static random access memory cell to receive and permanently retain the digital signal from the static random access memory cell; wherein the first EEPROM element comprises; a first floating gate tunnel oxide transistor comprising an control gate connected to an EEPROM word line for controlling activation of the first floating gate tunnel oxide transistor and a floating gate placed over a channel region between a drain and source of the first floating gate tunnel oxide transistor for permanently retaining the digital signal and placed over an insulating layer wherein the insulating layer has a first tunneling window placed in proximity to the source of the first floating gate tunnel oxide transistor for providing a path for transfer of charge between the floating gate and the source during erasing to set an erased threshold voltage level of the first floating gate tunnel oxide transistor and providing a path for transfer of charge between the floating gate and the channel for programming to set a programmed threshold voltage level of the first floating gate transistor, a first select gating transistor having a drain connected to the static random access memory cell, a source connected to the drain of the floating gate tunnel oxide transistor, and a gate connected to a first select gating signal for controlling access to the floating gate tunnel oxide transistor, and a second select gating transistor having a drain connected to the source of the floating gate tunnel oxide transistor, a source connected to a source line, and a control gate connected to a second select gating signal for controlling access between the floating gate tunnel oxide transistor and the source line. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58)
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59. A method for forming an integrated nonvolatile static random access memory comprises the steps of:
forming a plurality of integrated nonvolatile static random access memory circuits; connecting each of the static random access memory cells to one of a plurality first bit lines to receive and retain a digital signal indicative of a data bit; connecting each of the static random access memory cells to one of a plurality of complementary bit lines to receive and retain a complementary digital signal indicative of a complementary data bit; connecting each of the static random access memory cells to one of a plurality of SRAM word lines for controlling access to the one of the bit lines and complementary bit lines; forming a first EEPROM element for each of the integrated nonvolatile static random access memory circuits by the steps of; forming a first floating gate tunnel oxide transistor including an EEPROM control gate and a floating gate placed over a channel region between a drain and source of the first floating gate tunnel oxide transistor for permanently retaining the digital signal, connecting the control gate to one of a plurality of EEPROM word lines for controlling activation of the first floating gate tunnel oxide transistor, placing the floating gate over an insulating layer wherein the insulating layer has a first tunnel window placed in proximity to the source of the first floating gate tunnel oxide transistor for providing a path for transfer of charge between the floating gate and the source during erasing to set an erased threshold voltage level of the first floating gate tunnel oxide transistor and providing a path for transfer of charge between the floating gate and the channel for programming to set a programmed threshold voltage level of the first floating gate tunnel oxide transistor, forming a first select gating transistor having a drain connected to the static random access memory cell, a source connected to the drain of the first floating gate tunnel oxide transistor, and a gate connected to one of a plurality of first select gating signals for controlling access between the floating gate tunnel oxide transistor and the static random access memory cell, and forming a second select gating transistor having a drain connected to the source of the first floating gate tunnel oxide transistor, a source connected to one of a plurality of a source lines, and a control gate connected to one of a plurality of second select gating signals for controlling access to the first floating gate tunnel oxide transistor from the source line; arranging the plurality of integrated nonvolatile static random access memory circuits in an array of rows and columns. - View Dependent Claims (60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90)
Specification