Frequency detector and phase locked loop having the same
First Claim
Patent Images
1. A frequency detector comprising:
- an error measurement unit that measures a time interval between zero-crossing points of an input signal that is modulated to provide a measured time interval;
an error conversion unit that quantizes the measured time interval using one of modulation time intervals to provide a quantized time interval; and
an error calculation unit that calculates a frequency error based upon a difference between the measured time interval and the quantized time interval to provide a calculated frequency error,wherein the error measurement unit comprises;
a sampling unit that generates a first absolute value and a second absolute value respectively corresponding to the input signal and a delayed input signal at the sampling time points before and after a j-th zero-crossing point, where “
j”
is a natural number over 2;
a first linear interpolation unit that generates a first interpolation value based upon the first absolute value and the second absolute value;
a zero-crossing point detection unit that detects a zero-crossing point of each of the input signal and the delayed input signal and that measures the number of samplings between the j-th zero-crossing point and i-th zero-crossing point, “
i”
being a natural number greater than j, to provide a measured sampling number; and
a second linear interpolation unit that generates an interpolation value difference based upon the first interpolation value and a second interpolation value generated at the i-th zero-crossing point, and that generates the measured time interval based upon the measured sampling number and the interpolation value difference.
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Abstract
A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.
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Citations
20 Claims
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1. A frequency detector comprising:
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an error measurement unit that measures a time interval between zero-crossing points of an input signal that is modulated to provide a measured time interval; an error conversion unit that quantizes the measured time interval using one of modulation time intervals to provide a quantized time interval; and an error calculation unit that calculates a frequency error based upon a difference between the measured time interval and the quantized time interval to provide a calculated frequency error, wherein the error measurement unit comprises; a sampling unit that generates a first absolute value and a second absolute value respectively corresponding to the input signal and a delayed input signal at the sampling time points before and after a j-th zero-crossing point, where “
j”
is a natural number over 2;a first linear interpolation unit that generates a first interpolation value based upon the first absolute value and the second absolute value; a zero-crossing point detection unit that detects a zero-crossing point of each of the input signal and the delayed input signal and that measures the number of samplings between the j-th zero-crossing point and i-th zero-crossing point, “
i”
being a natural number greater than j, to provide a measured sampling number; anda second linear interpolation unit that generates an interpolation value difference based upon the first interpolation value and a second interpolation value generated at the i-th zero-crossing point, and that generates the measured time interval based upon the measured sampling number and the interpolation value difference. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A phase locked loop comprising:
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a first frequency detector that detects and outputs a first frequency error based upon a sync pulse of an input signal that is modulated in a first operational mode from a point in time when a supply of power starts to a point in time when a frequency of the input signal approaches a first frequency; a second frequency detector that detects and outputs a second frequency error based upon a data pulse of the input signal in a second operational mode from the point in time when the frequency of the input signal approaches the first frequency to a point in time when the frequency of the input signal approaches a second frequency; a phase detector that detects and outputs a third frequency error in the second operational mode and in a third operational mode from the point in time when the frequency of the input signal approaches the second frequency to a point in time when the frequency of the input signal approaches a locking frequency; and a loop filter that generates an accumulated frequency error in proportion to one of the first frequency error, the second frequency error, or the third frequency error that is received based upon the operational mode, wherein a locking operation with respect to the data signal is performed based upon the accumulated frequency error. - View Dependent Claims (16, 17, 18, 19)
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20. A signal processing device comprising:
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a first frequency detector that detects and outputs a first frequency error based upon a sync pulse of an input signal that is modulated in a first operational mode from a point in time when a supply of power starts to a point in time when a frequency of the input signal approaches a first frequency; a second frequency detector that detects and outputs a second frequency error based upon a data pulse of the input signal in a second operational mode from the point in time when the frequency of the input signal approaches the first frequency to a point in time when the frequency of the input signal approaches a second frequency; a phase detector that detects and outputs a third frequency error in the second operational mode and in a third operational mode from the point in time when the frequency of the input signal approaches the second frequency to a point in time when the frequency of the input signal approaches a locking frequency; a loop filter that generates an accumulated frequency error in proportion to one of the first frequency error, the second frequency error, or the third frequency error that is received based upon the operational mode, and a frequency error selection unit that selectively outputs a corresponding one of the first frequency error, the second frequency error, or the third frequency error based upon the operational mode to the loop filter, wherein a locking operation with respect to the data signal is performed based upon the accumulated frequency error, and wherein the input signal is an eight-to-fourteen modulation format (EFM) signal or an EFM+ signal.
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Specification