Frequency detector and phase locked loop having the same

• US 8,331,519 B2
• Filed: 04/27/2009
• Issued: 12/11/2012
• Est. Priority Date: 06/11/2008
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Zhidkov, Sergey, Huh, Jun Ho, Kwon, Ki Seop
• Primary Examiner(s): Lee, Siu
• Application Number:
  US12/430,691
• Publication Number:
  US 20090310730A1
• Time in Patent Office: 1,324 Days
• Field of Search: 375/316, 375/376, 375/354, 375/355, 375/357, 375/359, 375/360, 375/368, 375/371, 375/373, 375/375, 327/48, 327/156, 327/161
• US Class Current: 375/376
• CPC Class Codes: G01R 23/10 by converting frequency into a train of pulses, which are then counted , i.e. converting the signal into a square wave
• CPC Class Codes: G01R 23/15 Indicating that frequency of pulses is either above or below a predetermined value or within or outside a predetermined range of values, by making use of non-linear or digital elements (indicating that pulse width is above or below a certain limit)
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0998 using phase interpolation
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Claims

1. A frequency detector comprising:

an error measurement unit that measures a time interval between zero-crossing points of an input signal that is modulated to provide a measured time interval;

an error conversion unit that quantizes the measured time interval using one of modulation time intervals to provide a quantized time interval; and

an error calculation unit that calculates a frequency error based upon a difference between the measured time interval and the quantized time interval to provide a calculated frequency error,

wherein the error measurement unit comprises;

a sampling unit that generates a first absolute value and a second absolute value respectively corresponding to the input signal and a delayed input signal at the sampling time points before and after a j-th zero-crossing point, where “

j”

is a natural number over 2;

a first linear interpolation unit that generates a first interpolation value based upon the first absolute value and the second absolute value;

a zero-crossing point detection unit that detects a zero-crossing point of each of the input signal and the delayed input signal and that measures the number of samplings between the j-th zero-crossing point and i-th zero-crossing point, “

i”

being a natural number greater than j, to provide a measured sampling number; and

a second linear interpolation unit that generates an interpolation value difference based upon the first interpolation value and a second interpolation value generated at the i-th zero-crossing point, and that generates the measured time interval based upon the measured sampling number and the interpolation value difference.

2. The frequency detector of claim 1, further comprising an error generation control unit that controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

3. The frequency detector of claim 1, wherein the measured time interval is expressed by an equation:

4. The frequency detector of claim 1, wherein “

j”

is a natural number next to “

i”

.

5. The frequency detector of claim 1, wherein the sampling unit comprises:

a delay unit that receives the input signal, delays the received input signal for a predetermined time, and outputs the delayed input signal; and

an absolute value generation unit that generates the first absolute value and the second absolute value based upon values obtained by sampling the input signal and the delayed input signal at a predetermined time interval.

6. The frequency detector of claim 1, wherein the first linear interpolation unit comprises:

a first adder that receives the first absolute value and the second absolute value, sums the received first absolute value and second absolute value, and outputs a third absolute value;

a look-up table that receives the third absolute value and generates a reciprocal of the received third absolute value; and

a first multiplier that receives the second absolute value and the reciprocal of the third absolute value and generates the first interpolation value by multiplying the second absolute value and the reciprocal of the third absolute value.

7. The frequency detector of claim 1, wherein the zero-crossing point detection unit comprises:

a zero-crossing point detector that detects a zero-crossing point of each of the input signal and the delayed input signal; and

a counter that generates the measured sampling number by counting the number of samplings from the j-th zero-crossing point generation point in time to the i-th zero-crossing point generation point in time.

8. The frequency detector of claim 1, wherein the second linear interpolation unit comprises:

a register that receives and stores the first interpolation value in response to a generation of the j-th zero-crossing point, and outputs the second interpolation value;

a second adder that receives the first interpolation value and the second interpolation value and generates the interpolation value difference based upon the first interpolation value and the second interpolation value; and

a third adder that receives the interpolation value difference and the measured sampling number, sums the interpolation value difference and the measured sampling number, and generates the measured time interval.

9. The frequency detector of claim 1, wherein the error measurement unit further comprises a first selector that selectively outputs the measured time interval at a positive zero-crossing point or the measured time interval at a negative zero-crossing point.

10. The frequency detector of claim 1, wherein the error conversion unit quantizes the measured time interval using the closest time interval of the modulation time intervals.

11. The frequency detector of claim 1, wherein the frequency error is expressed by an equation:

12. The frequency detector of claim 2, wherein the error generation control unit comprises:

a first error generation control unit that generates a first control signal based upon whether the quantized time interval is within a predetermined time interval range;

a second error generation control unit that generates a second control signal based upon a result of a comparison between the calculated frequency error and the predetermined critical value; and

an error generation determination unit that controls whether to output the frequency error in response to the first control signal and the second control signal.

13. The frequency detector of claim 12, wherein the error generation control unit further comprises a sign detection unit that receives the frequency error and outputs only a sign value indicating a direction of the frequency error to the error generation determination unit.

14. The frequency detector of claim 2, further comprising an amplification unit that multiplies the frequency error output from the error generation control unit by a predetermined gain value and outputs a multiplied frequency error.

15. A phase locked loop comprising:

a first frequency detector that detects and outputs a first frequency error based upon a sync pulse of an input signal that is modulated in a first operational mode from a point in time when a supply of power starts to a point in time when a frequency of the input signal approaches a first frequency;

a second frequency detector that detects and outputs a second frequency error based upon a data pulse of the input signal in a second operational mode from the point in time when the frequency of the input signal approaches the first frequency to a point in time when the frequency of the input signal approaches a second frequency;

a phase detector that detects and outputs a third frequency error in the second operational mode and in a third operational mode from the point in time when the frequency of the input signal approaches the second frequency to a point in time when the frequency of the input signal approaches a locking frequency; and

a loop filter that generates an accumulated frequency error in proportion to one of the first frequency error, the second frequency error, or the third frequency error that is received based upon the operational mode,

wherein a locking operation with respect to the data signal is performed based upon the accumulated frequency error.

16. The phase locked loop of claim 15, further comprising a frequency error selection unit that selectively outputs a corresponding one of the first frequency error, the second frequency error, or the third frequency error based upon the operational mode to the loop filter.

17. The phase locked loop of claim 16, wherein the second frequency detector further comprises:

an error measurement unit that measures a time interval between zero-crossing points of the input signal to provide a measured time interval;

an error conversion unit that quantizes the measured time interval using one of modulation time intervals to provide a quantized time interval;

an error calculation unit that calculates a frequency error based upon a difference between the measured time interval and the quantized time interval to provide a calculated frequency error; and

an error generation control unit that controls whether to output the second frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

18. The phase locked loop of claim 15, wherein the loop filter is a second loop that comprises:

a first filter that outputs a fourth frequency error in proportion to the third frequency error;

a second filter that receives a corresponding one of the first frequency error, the second frequency error, or the third frequency error based upon the operational mode and outputs a fifth frequency error accumulated in proportion to the received frequency error; and

a first adder that generates the accumulated frequency error by receiving and summing the fourth frequency error and the fifth frequency error.

19. The phase locked loop of claim 18, wherein the second filter comprises:

a second adder that receives and sums the received frequency error and a delayed fifth frequency error to generate the fifth frequency error; and

a delay unit that generates the delayed fifth frequency error by receiving the fifth frequency error, delaying the received fifth frequency error for a predetermined time, and outputting the delayed fifth frequency error.

20. A signal processing device comprising:

a first frequency detector that detects and outputs a first frequency error based upon a sync pulse of an input signal that is modulated in a first operational mode from a point in time when a supply of power starts to a point in time when a frequency of the input signal approaches a first frequency;

a second frequency detector that detects and outputs a second frequency error based upon a data pulse of the input signal in a second operational mode from the point in time when the frequency of the input signal approaches the first frequency to a point in time when the frequency of the input signal approaches a second frequency;

a phase detector that detects and outputs a third frequency error in the second operational mode and in a third operational mode from the point in time when the frequency of the input signal approaches the second frequency to a point in time when the frequency of the input signal approaches a locking frequency;

a loop filter that generates an accumulated frequency error in proportion to one of the first frequency error, the second frequency error, or the third frequency error that is received based upon the operational mode, and

a frequency error selection unit that selectively outputs a corresponding one of the first frequency error, the second frequency error, or the third frequency error based upon the operational mode to the loop filter,

wherein a locking operation with respect to the data signal is performed based upon the accumulated frequency error, and

wherein the input signal is an eight-to-fourteen modulation format (EFM) signal or an EFM+ signal.