Power-saving receiver circuits, systems and processes
First Claim
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1. An electronic circuit comprisinga receiver circuit operable to perform coherent summations having a coherent summations time interval;
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Abstract
An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control circuit (2130) coupled to said receiver circuit (BSP) and operable to impress a power controlling duty cycle (TON, TOFF) on the receiver circuit (BSP) inside the coherent summations time interval. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.
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Citations
19 Claims
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1. An electronic circuit comprising
a receiver circuit operable to perform coherent summations having a coherent summations time interval; - and
a power control circuit coupled to said receiver circuit and operable to impress a power controlling duty cycle on the receiver circuit inside the coherent summations time interval. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A telecommunications device comprising
a spread spectrum receiver circuit operable to perform coherent summations having a coherent summations time interval; - and
a power control circuit coupled to said receiver circuit and operable to impress a power controlling duty cycle on the spread spectrum receiver circuit inside the coherent summations time interval. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification