Graphics processor with snoop filter

• US 8,332,592 B2
• Filed: 10/08/2004
• Issued: 12/11/2012
• Est. Priority Date: 10/08/2004
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hoover, Russell D., Mejdrich, Eric O.
• Primary Examiner(s): Lane, John
• Application Number:
  US10/961,750
• Publication Number:
  US 20060080512A1
• Time in Patent Office: 2,986 Days
• Field of Search: 711/141, 711/144, 711/146, 711/133
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means

Abstract

Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. The remote device may include coherency logic, referred to herein as a snoop filter, designed to filter memory access requests that do not require bus commands to be sent to the processor. The snoop filter may filter requests based on a remote cache directory designed to mirror the processor cache directory, such that only those requests that target cache lines indicated to be valid in the processor cache result in snoop commands sent to the processor. Other requests (targeting data that is not cached in the processor) may be routed directly to memory without the latency conventionally associated with snoop requests.

Claims

1. A method of maintaining coherency of data accessed by a remote device, comprising:

maintaining, on the remote device, a remote cache directory indicative of memory locations residing in a cache on a processor which shares access to some portion of a memory device;

routing a first memory request issued at the remote device to the memory device without sending snoop requests to the processor if information contained in the remote cache directory indicates a valid copy of data targeted by the request does not reside in the processor cache;

routing a second memory request to the memory device when the remote cache directory indicates that a memory location targeted by the second memory request is cached in an L2 cache in a shared coherency state; and

sending a bus command to the processor if information contained in the remote cache directory indicates a valid copy of data targeted by the first memory request resides in the processor cache.

2. The method of claim 1, wherein maintaining the remote cache directory comprises monitoring, at the remote device, requests to memory issued by the processor.

3. The method of claim 2, wherein maintaining the remote cache directory further comprises creating entries in the remote cache directory containing address tags for memory locations targeted by the memory requests and one or more coherency bits.

4. The method of claim 3, wherein the one or more coherency bits comprise a single bit indicating a valid or invalid coherency state.

5. The method of claim 1, wherein the bus command comprises a command to read data directly from the processor cache without accessing the memory device.

6. The method of claim 1, wherein the bus command comprises a command requesting the processor to invalidate or evict its copy of data targeted by the first memory request issued by the remote device.

7. The method of claim 1, wherein the remote cache directory supports valid, invalid, and shared coherency states.

8. The method of claim 1, further comprising sending a bus command to the processor if the remote cache directory indicates the memory location targeted by the second memory request is cached in the L2 cache in the shared coherency state.

9. A device configured to access data stored in memory and cacheable by a processor, comprising:

at least one processing core;

a remote cache directory indicative of contents of a processor cache residing on the processor; and

a snoop filter configured to;

route a first memory request issued by the processing core to a memory device without sending snoop requests to the processor if information contained in the remote cache directory indicates a valid copy of data targeted by the memory request does not reside in the processor cache;

route a second memory request to the memory device when the remote cache directory indicates that a memory location targeted by the second memory request is cached in an L2 cache in a shared coherency state; and

send a bus command to the processor if information contained in the remote cache directory indicates a valid copy of data targeted by the first memory request resides in the processor cache.

10. The device of claim 9, wherein the snoop logic is configured to:

monitor memory requests issued by the processor; and

in response, updates entries in the remote cache directory containing address tags for memory locations targeted by the memory requests and one or more coherency bits.

11. The device of claim 10, wherein the one or more bits comprise more than one bit to indicate valid, invalid and shared coherency states.

12. The device of claim 9, wherein the bus command comprises a command to read data directly from the processor cache without accessing the memory device.

13. The device of claim 9, wherein the bus command comprises a command requesting the processor to invalidate or evict its copy of data targeted by the first memory request issued by the processing core.

14. The device of claim 9, wherein the snoop filter is configured to route the first and second memory requests to the memory device via a memory controller residing on the remote device.

15. A coherent system, comprising:

a processor comprising a cache for storing data accessed from an external memory device and a cache directory with entries indicating which memory locations are stored in cache lines of the cache and corresponding coherency states thereof; and

a remote device comprising a remote cache directory indicative of contents of the cache residing on the processor and a snoop filter configured to;

route a first memory request issued at the remote device to the memory device without sending snoop requests to the processor if information contained in the remote cache directory indicates a valid copy of data targeted by the memory request does not reside in the processor cache;

route a second memory request to the memory device when the remote cache directory indicates that a memory location targeted by the second memory request is cached in an L2 cache in a shared coherency state; and

send a bus command to the processor if information contained in the remote cache directory indicates a valid copy of data targeted by the first memory request resides in the processor cache.

16. The system of claim 15, wherein the remote device is a graphics processing unit (GPU) including one or more graphics processing cores.

17. The system of claim 15, wherein the snoop filter is configured to:

monitor memory requests issued by the processor; and

in response, updates entries in the remote cache directory containing address tags for memory locations targeted by the memory requests and one or more coherency bits.