Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same

• US 8,332,792 B2
• Filed: 07/14/2010
• Issued: 12/11/2012
• Est. Priority Date: 07/14/2010
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Tetelbaum, Alexander, Zahn, Bruce, Jamann, Joseph, Laubhan, Rich
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US12/836,274
• Publication Number:
  US 20120017190A1
• Time in Patent Office: 881 Days
• Field of Search: 716/108, 716/113, 716/114
• US Class Current: 716/113
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3) determining a minimum ramptime limit between the frequency based ramptime limit and the library based ramptime limit and (4) selecting the minimum ramptime limit as the flexible ramptime limit.

Claims

1. A method of generating flexible ramptime limits for an electronic circuit, comprising:

calculating a frequency based ramptime limit for each data signal and clock signal of said electronic circuit;

obtaining a library based ramptime limit for each said data signal and said clock signal of said electronic circuit;

determining a minimum ramptime limit between said frequency based ramptime limit and said library based ramptime limit for each said data signal and said clock signal; and

selecting said minimum ramptime limit, using a processor, as said flexible ramptime limit for each said data signal and said clock signal.

2. The method as recited in claim 1 wherein each said data signal traverses a data net of said electronic circuit.

3. The method as recited in claim 2 wherein each said clock signal traverses a clock net of said electronic circuit.

4. The method as recited in claim 3 wherein said electronic circuit includes multiple data nets and multiple clock nets.

5. The method as recited in claim 1 wherein said library based ramptime limit is a Library Characterization Ramptime Limit for a type of cell that is associated with a data net or a clock net of said electronic circuit.

6. The method as recited in claim 1 wherein said frequency based ramptime limit is a function of a period for a data signal or a clock signal of said electronic circuit.

7. The method as recited in claim 1 wherein said calculating, said determining and said selecting are performed automatically.

8. An apparatus, comprising:

a ramptime limit generator configured to calculate a frequency based ramptime limit and obtain a library based ramptime limit for a net of an electronic circuit;

a flexible ramptime limit selector configured to determine a minimum ramptime limit between said frequency based ramptime limit and said library based ramptime limit and select said minimum ramptime limit as a flexible ramptime limit for said net.

9. The apparatus as recited in claim 8 wherein said net is a data net.

10. The apparatus as recited in claim 8 wherein said net is a clock net.

11. The apparatus as recited in claim 8 wherein said net has a cell driver and said library based ramptime limit is a Library Characterization Ramptime Limit for a type of said cell driver.

12. The apparatus as recited in claim 8 wherein said frequency based ramptime limit is a function of a clock period for a signal that traverses said net.

13. The apparatus as recited in claim 8 wherein said ramptime limit generator is configured to automatically calculate said frequency based ramptime limit and automatically obtain said library based ramptime limit.

14. The apparatus as recited in claim 8 wherein said flexible ramptime limit selector is configured to automatically determine a minimum ramptime limit between said frequency based ramptime limit and said library based ramptime limit and automatically select said minimum ramptime limit as a flexible ramptime limit for said net.

15. The apparatus as recited in claim 8 wherein said apparatus is an Electronic Design Automation tool.

16. A computer program product, comprising a non-transitory computer readable medium having a series of operating instructions embodied therein, said series of operating instructions adapted to be executed to implement a method of generating flexible ramptime limits, comprising:

calculating a frequency based ramptime limit for each data signal and clock signal of said electronic circuit;

obtaining a library based ramptime limit for each said data signal and said clock signal of said electronic circuit;

determining a minimum ramptime limit between said frequency based ramptime limit and said library based ramptime limit for each said data signal and said clock signal; and

selecting said minimum ramptime limit as said flexible ramptime limit for each said data signal and said clock signal.