Microchips with multiple internal hardware-based firewalls and dies

• US 8,332,924 B2
• Filed: 06/30/2008
• Issued: 12/11/2012
• Est. Priority Date: 11/29/1996
• Status: Expired due to Fees

• Current Assignee: Frampton E. Ellis
• Original Assignee: Frampton E. Ellis
• Inventors: Ellis, Frampton E.
• Primary Examiner(s): Reza, Mohammad W
• Application Number:
  US12/164,661
• Publication Number:
  US 20090031412A1
• Time in Patent Office: 1,625 Days
• Field of Search: 726/11, 726/12, 726/13, 726/14, 713/100, 713/151, 713/153, 713/154
• US Class Current: 726/11
• CPC Class Codes: A01N 25/30 characterised by the surfactants
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16
• CPC Class Codes: G06F 21/00 Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
• CPC Class Codes: G06F 9/5072 Grid computing
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 63/02 for separating internal from external traffic, e.g. firewalls
• CPC Class Codes: H04L 63/0209 Architectural arrangements, e.g. perimeter networks or demilitarized zones
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 69/14 Multichannel or multilink protocols
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: Y04S 40/00 Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them

Abstract

A microchip comprising a first internal hardware-based firewall configured to deny access to a first portion of the microchip from a network; a general purpose microprocessor including two general purpose cores or general purpose processing units; at least two dies having been made by a separate fabrication processes and assembled into a package with separate die sections connected directly; and a memory component located inside of a second internal hardware-based firewall that is located between the memory component and one of the cores or processing units with which the memory component is associated. Wherein a first core is located within the first microchip portion protected by the first firewall; a second core is located within a second microchip portion not protected by the first firewall; and the second core is separated from the first core by the first firewall and is located between the first firewall and the network.

Claims

1. A microchip for a computer configured to connect to at least one network of computers, said microchip comprising:

at least a first internal hardware-based firewall, said first internal hardware-based firewall configured to deny access to at least a portion of said microchip from said network;

at least one general purpose microprocessor including at least two general purpose cores or general purpose processing units;

a plurality of dies, at least two of said dies made by a separate fabrication process and assembled into a package with separate die sections connected directly; and

at least one memory component located inside of at least a second internal hardware-based firewall that is located between said memory component and at least one said core or processing unit with which said memory component is associated; and

wherein

at least a first said core or processing unit is located within said first portion of said microchip that is protected by at least said first internal hardware-based firewall;

at least a second said core or processing unit is located within a second portion of said microchip that is not protected by at least said first internal hardware-based firewall; and

at least said second core or processing unit is separated from said first core or processing unit by at least said first internal hardware-based firewall and is located between at least said first internal hardware-based firewall and said at least one network of computers.

2. The microchip of claim 1, wherein said microchip is surrounded by at least one Faraday Cage.

3. The microchip of claim 2, wherein said microchip includes a plurality of Faraday Cages.

4. The microchip of claim 1, wherein said microchip includes at least three or more said cores or processing units, each located within a portion of said microchip protected by at least one internal hardware-based firewall.

5. The microchip of claim 1, wherein at least one control unit is protected by at least one of said internal hardware-based firewalls and said at least one control unit controls said cores or processing units.

6. The microchip of claim 1, wherein said microchip includes at least three or more said cores or processing units, at least two said cores or processing units being protected by at least one said internal hardware-based firewall.

7. The microchip of claim 1, wherein said second core or processing unit is located within a portion of said microchip protected by at least a third internal hardware firewall.

8. A microchip for a computer configured to connect to at least one network of computers, said microchip comprising:

at least four internal hardware-based firewalls, said internal hardware-based firewalls configured to deny access to at least four portions of said microchip from said network;

at least one general purpose microprocessor with at least four general purpose cores or general purpose processing units;

at least three of said cores or said processing units are each located within one said portion of said microchip that is protected by at least one of three separate internal hardware-based firewalls; and

at least a fourth said core or said processing unit is located within a portion of said microchip that is not protected by at least said three separate internal hardware-based firewalls, at least said fourth core or processing unit is separated from said first core or processing unit by at least said three separate internal hardware-based firewalls and is located between at least said three separate internal hardware-based firewalls and said at least one network of computers;

a plurality of dies, at least two of said dies made by a separate fabrication process and assembled into a package with separate die sections connected directly; and

at least one memory component located within said portion of said microchip that is protected by at least said fourth separate internal hardware-based firewall that is located between said memory component and at least one said core or processing unit with which said memory component is associated.

9. The microchip of claim 8, wherein said microchip is surrounded by at least one Faraday Cage.

10. The microchip of claim 9, wherein said microchip includes a plurality of Faraday Cages.

11. The microchip of claim 8, wherein at least one control unit is protected by at least one of said three separate internal hardware-based firewalls, and said at least one control unit controls said cores or processing units.

12. A microchip for a computer configured to connect to at least one network of computers, said microchip comprising:

at least a first internal hardware-based firewall, said first internal hardware-based firewall configured to deny access to at least a portion of said microchip from said network;

at least one general purpose microprocessor with at least one control unit and at least two general purpose cores or general purpose processing units, said control unit being configured to control said at least two cores or processing units;

a plurality of dies, at least two of said dies made by a separate fabrication process and assembled into a package with separate die sections connected directly; and

at least one memory component located inside of at least a second internal hardware-based firewall that is located between said memory component and at least one said core or processing unit with which said memory component is associated; and

wherein

at least said control unit and a first said core or processing unit is located within said portion of said microchip that is protected by at least said first internal hardware-based firewall;

at least a second said core or processing unit is located within a portion of said microchip that is not protected by at least said first internal hardware-based firewall; and

at least said second core or processing unit is separated from said first core or processing unit by said first internal hardware-based firewall and is located between said first internal hardware-based firewall and said at least one network of computers.

13. The microchip of claim 12, wherein said microchip is surrounded by a plurality of Faraday Cages.

14. The microchip of claim 12, wherein said microchip includes three or more internal hardware-based firewalls.

15. The microchip of claim 12, where said microchip is surrounded by a Faraday cage.

16. The microchip of claim 12, wherein said microchip includes at least three or more said cores or processing units, each protected by at least one said internal hardware-based firewall.

17. The microchip of claim 12, wherein said microchip includes at least three or more said cores or processing units, at least two said cores or processing units being protected by at least one said internal hardware-based firewall.

18. The microchip of claim 12, wherein said second core or processing unit is located within a portion of said microchip protected by at least a third internal hardware firewall.