Bottom electrode etching process in MRAM cell

• US 8,334,213 B2
• Filed: 06/05/2009
• Issued: 12/18/2012
• Est. Priority Date: 06/05/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: MagiQ Technologies, Incorporated
• Inventors: Mao, Guomin
• Primary Examiner(s): Ahmed, Shamim
• Assistant Examiner(s): Gates, Bradford
• Application Number:
  US12/455,757
• Publication Number:
  US 20100311243A1
• Time in Patent Office: 1,292 Days
• Field of Search: None
• US Class Current: 438/704
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

A BE patterning scheme in a MRAM is disclosed that avoids damage to the MTJ array and underlying ILD layer while reducing BE-BE shorts and BE-bit line shorts. A protective dielectric layer is coated over a MTJ array before a photoresist layer is coated and patterned on the dielectric layer. The photoresist pattern is transferred through the dielectric layer with a dielectric etch process and then through the BE layer with a metal etch that includes a certain amount of overetch to remove metal residues. The photoresist is stripped with a sequence involving immersion or spraying with an organic solution followed by oxygen ashing to remove any other organic materials. Finally, a second wet strip is performed with a water based solution to provide a residue free substrate. In another embodiment, a bottom anti-reflective coating (BARC) is inserted between the photoresist and dielectric layer for improved critical dimension control.

Claims

1. A method of patterning a bottom electrode layer in a MRAM structure, said bottom electrode layer is formed on a substrate including an insulation layer dielectric (ILD), comprising:

(a) providing an array of MTJ elements on said bottom electrode layer wherein each of said MTJ elements has a bottom portion contacting the bottom electrode layer, a top portion having a top surface, and sidewalls connecting said top surface to the bottom electrode layer;

(b) forming a protective dielectric layer that serves as a hard mask on the top surface and sidewalls of the MTJ elements and on the bottom electrode layer between adjacent MTJ elements;

(c) forming a stack of layers on the protective dielectric layer, comprising;

(1) a bottom anti-reflective coating (BARC) which contacts the protective dielectric layer; and

(2) a photoresist layer on the BARC layer;

(d) patterning the photoresist layer to form a plurality of openings between adjacent MTJ elements;

(e) transferring said plurality of openings through the BARC layer and through the protective dielectric layer with a dielectric etch process;

(f) transferring said plurality of openings through the bottom electrode layer with a metal etch process to form a patterned bottom electrode below each of said plurality of MTJ elements, said metal etch includes a certain amount of overetching that removes a top portion of the ILD at the bottom of each of the plurality of openings; and

(g) removing the photoresist and BARC layers following the metal etch through the bottom electrode, the photoresist and BARC are removed with a stripping process that is a sequence of wet, dry, and wet stripping methods, comprising;

(1) a first method which is a first wet strip that includes immersing or spraying the substrate with a solution including one or more organic solvents;

(2) a dry ashing step following the first wet strip that includes exposing the substrate to an O₂ plasma; and

(3) a second wet strip following the dry ashing step that includes treatment of the substrate with a water based solution.

2. The method of claim 1 wherein the protective dielectric layer has a thickness between about 200 and 1000 Angstroms.

3. The method of claim 1 wherein the bottom electrode layer is comprised of Ta and has a thickness from about 100 to 600 Angstroms.

4. The method of claim 1 wherein transferring the plurality of openings through the BARC layer and dielectric layer is performed in a dielectric etch chamber with a process comprising a fluorocarbon gas flow rate of about 20 to 200 standard cubic centimeters per minute (sccm), a N₂ flow rate between 0 and about 200 sccm, a pressure from about 20 to 250 mTorr, and a bias power in the range of about 100 to 800 Watts.

5. The method of claim 1 wherein transferring the plurality of openings through the bottom electrode layer is performed in a metal etch chamber with a process comprising a Cl₂ flow rate of about 20 to 120 sccm, a N₂ flow rate between about 10 and 80 sccm, a pressure from about 3 to 20 mTorr, a bias power in the range of about 20 to 100 Watts, and a source power from about 500 to 1600 Watts.

6. The method of claim 1 wherein the first wet strip consists of applying NMP maintained at a temperature between about 60°

C. and 90°

C.

7. The method of claim 1 wherein the second wet strip comprises a water based cleaning solution maintained at a temperature of about 30°

C. to 50°

C.

8. A method of patterning a bottom electrode layer in a MRAM structure, said bottom electrode layer is formed on a substrate including an insulation layer dielectric (ILD), comprising:

(a) providing an array of MTJ elements on said bottom electrode layer wherein each of said MTJ elements has a bottom portion contacting the bottom electrode layer, a top portion having a top surface, and sidewalls connecting said top surface to the bottom electrode layer;

(b) forming a dielectric anti-reflective coating (DARC) that also serves as a hard mask on the top surface and sidewalls of the MTJ elements and on the bottom electrode layer between adjacent MTJ elements;

(c) forming a photoresist layer on the DARC layer;

(d) patterning the photoresist layer to form a plurality of openings wherein there is an opening between adjacent MTJ elements;

(e) transferring said plurality of openings through the DARC layer with a dielectric etch process;

(f) transferring said plurality of openings through the bottom electrode layer with a metal etch process to form a patterned bottom electrode below each of the MTJ elements in said array, said metal etch includes a certain amount of overetch to remove a top portion of the ILD at the bottom of each of the plurality of openings; and

(g) removing the photoresist layer following the metal etch through the bottom electrode, the photoresist layer is removed with a stripping process that is a sequence of wet, dry, and wet stripping methods, comprising;

(1) a first method which is a first wet strip that includes immersing or spraying the substrate with a solution including one or more organic solvents;

(2) a dry ashing step following the first wet strip that includes exposing the substrate to an O₂ plasma; and

(3) a second wet strip following the dry ashing step that includes treatment of the substrate with a water based solution.

9. The method of claim 8 wherein the DARC is comprised of silicon oxynitride.

10. The method of claim 8 wherein the bottom electrode layer is comprised of Ta and has a thickness from about 100 to 600 Angstroms.

11. The method of claim 8 wherein transferring the plurality of openings through the DARC layer is performed in a dielectric etch chamber with a process comprising a fluorocarbon gas flow rate of about 20 to 200 standard cubic centimeters per minute (sccm), a N₂ flow rate between 0 and about 200 sccm, a pressure from about 20 to 250 mTorr, and a bias power in the range of about 100 to 800 Watts.

12. The method of claim 8 wherein transferring the plurality of openings through the bottom electrode layer is performed in a metal etch chamber with a process comprising a Cl₂ flow rate of about 20 to 120 sccm, a N₂ flow rate between about 10 and 80 sccm, a pressure from about 3 to 20 mTorr, a bias power in the range of about 20 to 100 Watts, and a source power from about 500 to 1600 Watts.

13. The method of claim 8 wherein the first wet strip consists of applying NMP maintained at a temperature between about 60°

C. and 90°

C.

14. The method of claim 8 wherein the second wet strip comprises a water based cleaning solution maintained at a temperature of about 30°

C. to 50°

C.

15. A method of patterning a bottom electrode layer in a MRAM structure, said bottom electrode layer is formed on a substrate including an insulation layer dielectric (ILD), comprising:

(a) providing an array of MTJ elements on said bottom electrode layer wherein each of said MTJ elements has a bottom portion contacting the bottom electrode layer, a top portion having a top surface, and sidewalls connecting said top surface to the bottom electrode layer;

(b) forming a spin-on carbon containing hard mask (C-SOH) on the top surface and sidewalls of the MTJ elements and on the bottom electrode layer between adjacent MTJ elements;

(c) forming a spin-on silicon containing hard mask (Si-SOH) on the C-SOH layer;

(d) forming a photoresist layer on the Si-SOH layer and patterning the photoresist layer to form a plurality of openings wherein there is an opening between adjacent MTJ elements;

(e) transferring said plurality of openings through the Si-SOH layer with a first dielectric etch process and through the C-SOH layer with a second dielectric etch process;

(f) transferring said plurality of openings through the bottom electrode layer with a metal etch process to form a patterned bottom electrode below each of the MTJ elements in said array, said metal etch includes a certain amount of overetch to remove a top portion of the ILD at the bottom of each of the plurality of openings; and

(g) removing the photoresist layer following the metal etch through the bottom electrode with a stripping process that is a sequence of wet, dry, and wet stripping methods, comprising;

(1) a first method which is a first wet strip that includes immersing or spraying the substrate with a solution including one or more organic solvents;

(2) a dry ashing step following the first wet strip that includes exposing the substrate to an O₂ plasma; and

(3) a second wet strip following the dry ashing step that includes treatment of the substrate with a water based solution.

16. The method of claim 15 wherein the first dielectric etch process is comprised of a fluorocarbon plasma.

17. The method of claim 15 wherein the second dielectric etch process is comprised of an oxygen plasma.

18. The method of claim 15 wherein the bottom electrode layer is comprised of Ta and has a thickness from about 100 to 600 Angstroms.

19. The method of claim 15 wherein transferring the plurality of openings through the bottom electrode layer is performed in a metal etch chamber with a process comprising a Cl₂ flow rate of about 20 to 120 sccm, a N₂ flow rate between about 10 and 80 sccm, a pressure from about 3 to 20 mTorr, a bias power in the range of about 20 to 100 Watts, and a source power from about 500 to 1600 Watts.

20. The method of claim 15 wherein the first wet strip consists of applying NMP maintained at a temperature between about 60°

C. and 90°

C. and the second wet strip comprises a water based cleaning solution maintained at a temperature of about 30°

C. to 50°

C.