SiC semiconductor device

• US 8,334,541 B2
• Filed: 07/07/2011
• Issued: 12/18/2012
• Est. Priority Date: 07/16/2010
• Status: Active Grant

• Current Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Sugimoto, Masahiro, Watanabe, Yukihiko, Miyahara, Shinichiro, Takaya, Hidefumi, Morimoto, Jun
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US13/177,747
• Publication Number:
  US 20120012860A1
• Time in Patent Office: 530 Days
• Field of Search: 438/931, 257/76, 257/77, 257/288, 257/E27.06, 257/E27.099
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A SiC semiconductor device includes a reverse type MOSFET having: a substrate; a drift layer and a base region on the substrate; a base contact layer and a source region on the base region; multiple trenches having a longitudinal direction in a first direction penetrating the source region and the base region; a gate electrode in each trench via a gate insulation film; an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed; a source electrode coupling with the source region and the base region through the contact hole; a drain electrode on the substrate. The source region and the base contact layer extend along with a second direction perpendicular to the first direction, and are alternately arranged along with the first direction. The contact hole has a longitudinal direction in the first direction.

Claims

1. A SiC semiconductor device comprising:

a reverse type MOSFET,

wherein the MOSFET includes;

a substrate having a first conductive type or a second conductive type and made of SIC;

a drift layer having the first conductive type and made of SiC, wherein the drift layer is disposed on the substrate and has an impurity concentration lower than the substrate;

a base region having the second conductive type and made of SiC, wherein the base region is disposed on the drift layer;

a base contact layer having the second conductive type and made of SiC, wherein the base contact layer is disposed on the base region and has an impurity concentration higher than the base region;

a source region having the first conductive type and made of SiC, wherein the source region is disposed on the base region and has an impurity concentration higher than the drift layer;

a plurality of trenches having a stripe pattern in a first direction as a longitudinal direction of the stripe pattern, wherein each trench is disposed on a surface of the source region, penetrates the base region and reaches the drift layer;

a gate insulation film disposed on an inner wall of each trench;

a gate electrode disposed on the gate insulation film in each trench;

an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed from the interlayer insulation film;

a source electrode electrically coupling with the source region and the base region through the contact hole; and

a drain electrode disposed on the substrate and opposite to the drift layer,

wherein the MOSFET provides a reverse channel area in a surface portion of the base region, which is disposed on a sidewall of each trench,

wherein the MOSFET controls an application voltage to the gate electrode so that the reverse channel area is generated, and the MOSFET flows current between the source electrode and the drain electrode via the source region and the drift layer,

wherein the source region and the base contact layer extend along with a second direction, which is perpendicular to the first direction,

wherein the source region and the base contact layer are alternately arranged along with the first direction, and

wherein the contact hole has a longitudinal direction in the first direction.

2. The SiC semiconductor device according to claim 1,

wherein the base contact layer contacts the sidewall of each trench, and

wherein the base contact layer is arranged between two adjacent trenches so as to join the two adjacent trenches.

3. The SIC semiconductor device according to claim 2,

wherein the plurality of trenches are arranged in parallel to each other along with the second direction,

wherein the MOSFET further includes a plurality of cells, and

wherein one of the cells is provided by:

the substrate;

the drift layer;

the base region disposed on both sides of a corresponding trench;

the base contact layer and the source region disposed on both sides of the corresponding trench;

the gate insulation film in the corresponding trench;

the gate electrode on the gate insulation film in the corresponding trench;

the interlayer insulation film covering the gate electrode;

the source electrode; and

the drain electrode.

4. The SiC semiconductor device according to claim 1,

wherein the base contact layer is spaced apart from the sidewall of each trench, and

wherein the source region is disposed between the sidewall of the trench and the base contact layer.

5. The SiC semiconductor device according to claim 1, further comprising:

a deep layer having the second conductive type,

wherein the deep layer is disposed in a portion of the drift layer under the base region,

wherein the deep layer has a bottom, which is deeper than a bottom of the trench,

wherein the deep layer extends along with the second direction, and

wherein the deep layer is arranged opposite to the base contact layer.

6. A SiC semiconductor device comprising:

an accumulation type MOSFET,

wherein the MOSFET includes;

a substrate having a first conductive type or a second conductive type and made of SiC;

a drift layer having the first conductive type and made of SiC, wherein the drift layer is disposed on the substrate and has an impurity concentration lower than the substrate;

a base region having the second conductive type and made of SiC, wherein the base region is disposed on the drift layer;

a base contact layer having the second conductive type and made of SiC, wherein the base contact layer is disposed on the base region and has an impurity concentration higher than the base region;

a source region having the first conductive type and made of SiC, wherein the source region is disposed on the base region and has an impurity concentration higher than the drift layer;

a plurality of trenches having a stripe pattern in a first direction as a longitudinal direction of the stripe pattern, wherein each trench is disposed on a surface of the source region, penetrates the base region and reaches the drift layer;

a gate insulation film disposed on an inner wall of each trench;

a channel layer having the first conductive type and made of SiC, wherein the channel layer is disposed between the gate insulation film and the base region in each trench;

a gate electrode disposed on the gate insulation film in each trench;

an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed from the interlayer insulation film;

a source electrode electrically coupling with the source region and the base region through the contact hole; and

a drain electrode disposed on the substrate and opposite to the drift layer,

wherein the MOSFET controls an application voltage to the gate electrode so that an accumulation type generated in the channel layer is controlled, and the MOSFET flows current between the source electrode and the drain electrode via the source region and the drift layer,

wherein the source region and the base contact layer extend along with a second direction, which is perpendicular to the first direction,

wherein the source region and the base contact layer are alternately arranged along with the first direction, and

wherein the contact hole has a longitudinal direction in the first direction.

7. The SiC semiconductor device according to claim 6,

wherein the base contact layer contacts the sidewall of each trench, and

wherein the base contact layer is arranged between two adjacent trenches so as to join the two adjacent trenches.

8. The SiC semiconductor device according to claim 7,

wherein the plurality of trenches are arranged in parallel to each other along with the second direction,

wherein the MOSFET further includes a plurality of cells, and

wherein one of the cells is provided by:

the substrate;

the drift layer;

the base region disposed on both sides of a corresponding trench;

the base contact layer and the source region disposed on both sides of the corresponding trench;

the gate insulation film in the corresponding trench;

the gate electrode on the gate insulation film in the corresponding trench;

the interlayer insulation film covering the gate electrode;

the source electrode; and

the drain electrode.

9. The SiC semiconductor device according to claim 6,

wherein the base contact layer is spaced apart from the sidewall of each trench, and

wherein the source region is disposed between the sidewall of the trench and the base contact layer.

10. The SiC semiconductor device according to claim 6, further comprising:

a deep layer having the second conductive type,

wherein the deep layer is disposed in a portion of the drift layer under the base region,

wherein the deep layer has a bottom, which is deeper than a bottom of the trench,

wherein the deep layer extends along with the second direction, and

wherein the deep layer is arranged opposite to the base contact layer.