Method to fabricate self-aligned source and drain in split gate flash

• US 8,334,558 B2
• Filed: 04/22/2003
• Issued: 12/18/2012
• Est. Priority Date: 02/26/2002
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsieh, Chia-Ta
• Primary Examiner(s): Booth, Richard A.
• Application Number:
  US10/420,594
• Publication Number:
  US 20030201502A1
• Time in Patent Office: 3,528 Days
• Field of Search: 257315-321
• US Class Current: 257/316
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A new structure is disclosed for source/drain bit lines in arrays of MOSFET devices. Rows of conducting regions are formed by ion implantation through openings adjacent to gate structures and in isolation regions separating columns of active areas of the arrays. The openings are filled with insulating material.

Claims

1. A new structure for source/drain bit lines in arrays of MOSFET devices comprising:

rows of conducting regions formed in a substrate under openings and below oxide filled isolation regions separating columns of active areas of said arrays;

insulating materials in said openings, wherein said openings are adjacent to gate structures and on said oxide filled isolation regions and wherein each of said openings has a bottom adjoining one of said conducting regions.

2. The structure of claim 1 wherein said MOSFET devices are n-channel devices and said conducting regions are formed to be n-type.

3. The structure of claim 1 wherein said MOSFET devices are p-channel devices and said conducting regions are formed to be p-type.

4. The structure of claim 1 wherein said insulating materials are oxide.

5. The structure of claim 1 wherein said insulating materials are high temperature oxide.

6. The structure of claim 1 wherein each of the said gate structures further comprises:

a floating gate oxide layer;

a first poly layer deposited on the floating gate oxide layer;

a dielectric separator layer deposited on the first poly layer;

a second poly layer deposited on the dielectric separator layer; and

a nitride layer deposited on the second poly layer.

7. The structure of claim 1 wherein the dielectric separator layer is a oxide/nitride/oxide (ONO) layer.

8. The structure of claim 1 wherein material of the nitride layer is Silicon Nitride.

9. The structure of claim 6 wherein the said gate structures further comprises:

an erasing gate oxide formed on the sidewalls of the gate structures; and

an erasing gate formed on the erasing gate oxide and the nitride layer.

10. A flash memory circuit comprising:

arrays of MOSFET devices; and

a plurality of source/drain bit lines in the arrays of MOSFET devices;

the source/drain bit lines being provided according to the structure of claim 1.