Semiconductor power device having shielding electrode for improving breakdown voltage

• US 8,334,566 B2
• Filed: 07/01/2010
• Issued: 12/18/2012
• Est. Priority Date: 03/29/2010
• Status: Active Grant

• Current Assignee: Sinopower Semiconductor, Inc.
• Original Assignee: Sinopower Semiconductor, Inc.
• Inventors: Tai, Sung-Shan
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US12/829,349
• Publication Number:
  US 20110233659A1
• Time in Patent Office: 901 Days
• Field of Search: 257/330, 257/331, 257/334, 257/341, 257/394, 257/401, 257/E21.19, 257/E29.262
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present invention provides a semiconductor power device including a substrate, an epitaxial layer disposed on the substrate and having at least a first trench and a second trench, a gate structure disposed in the first trench, and a termination structure disposed in the second trench. The gate structure includes a gate electrode, a gate dielectric layer disposed on an upper sidewall of the first trench and between the gate electrode and the epitaxial laver, and a shield electrode disposed under the gate electrode. The termination structure includes a termination electrode and a dielectric layer disposed between the termination electrode and a sidewall of the second trench. The termination electrode and the shield electrode are connected to each other. In addition, a body region is disposed in the epitaxial layer, and the second trench is only surrounded by the body region.

Claims

1. A semiconductor power device, comprising:

a substrate;

an epitaxial layer, disposed on the substrate, wherein the epitaxial layer comprises at least a first trench and a second trench;

a gate structure disposed in the first trench, the gate structure comprising;

a shield electrode and a gate electrode, the shield electrode being disposed under the gate electrode; and

a gate dielectric layer, disposed on an upper sidewall of the first trench and between the gate electrode and the epitaxial layer;

a termination structure disposed in the second trench, the termination structure comprising;

a termination electrode, wherein the termination electrode and the shield electrode are connected to each other; and

a dielectric layer disposed between the termination electrode and a sidewall of the second trench; and

a body region disposed in the epitaxial layer, wherein the second trench is only surrounded by the body region.

2. The semiconductor power device of claim 1, wherein the second trench extends into the substrate.

3. The semiconductor power device of claim 1, further comprising a doped region disposed under the second trench.

4. The semiconductor power device of claim 3, wherein a conductive type of the doped region and a conductive type of the epitaxial layer are the same.

5. The semiconductor power device of claim 1, wherein the epitaxial layer comprises the body region and a source region around the first trench, and the semiconductor power device further comprises an inter-layer dielectric layer to cover the source region, the gate electrode, and the gate dielectric layer.

6. The semiconductor power device of claim 5, wherein the Inter-layer dielectric layer and the gate dielectric layer comprise a plurality of contact holes to respectively expose the source region, the termination electrode, and the gate electrode.

7. The semiconductor power device of claim 6, further comprising a source metal layer disposed on the inter-layer dielectric layer, wherein the source metal layer is electrically connected to the source region through the contact hole of exposing the source region, and the source metal layer is electrically connected to the termination electrode through the contact hole of exposing the termination electrode.

8. The semiconductor power device of claim 6, further comprising a gate metal layer disposed on the inter-layer dielectric layer, wherein the gate metal layer is electrically connected to the gate electrode through the contact hole of exposing the gate electrode.