Semiconductor memory device capable of shortening erase time

• US 8,335,114 B2
• Filed: 06/16/2011
• Issued: 12/18/2012
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shibata, Noboru
• Primary Examiner(s): DINH, SON T
• Application Number:
  US13/162,051
• Publication Number:
  US 20110242903A1
• Time in Patent Office: 551 Days
• Field of Search: 365/185.29, 365/185.22, 365/185.18, 365/185.19
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

Claims

1. A semiconductor memory device comprising:

a memory cell array in which a plurality of memory cells are arranged in a matrix;

a plurality of word lines connected to the plurality of memory cells;

a plurality of bit lines connected to each of one end of the memory cells; and

a control circuit configured to control the potentials of said plurality of word lines and said plurality of bit lines,

wherein the control circuit sets a first voltage to first word lines of k (k is a natural number) of the plurality of word lines in an erase verify operation, sets a second voltage to second word lines of h (h is a natural number) of the plurality of word lines, and carries out the erase verify operation,

wherein the memory cells constitute a plurality of blocks as an erase unit, and

wherein the memory cells in the blocks are series-connected and which constitutes a series circuit, the second word lines are connected to the memory cells arranged at both ends of the series circuit, and the first word lines are connected to the another memory cells of the series circuit.

2. The semiconductor memory device according to claim 1, wherein the first word lines are adjacent to the second word lines.

3. The semiconductor memory device according to claim 1, further comprising:

second transistors connected to each of the second word lines, wherein a voltage which is step-upped is supplied to a gate electrode of the second transistors.

4. The semiconductor memory device according to claim 1, further comprising:

first transistors connected to each of the first word lines in the block, wherein a voltage which is step-upped is supplied to a gate electrode of the first transistors.

5. The semiconductor memory device according to claim 3, further comprising:

first transistors connected to each of the first word lines in the block,

wherein the gate electrode of the first transistors and the gate electrode of the second transistors are connected in common.

6. The semiconductor memory device according to claim 4, further comprising:

second transistors connected to each of the second word lines,

wherein the gate electrode of the first transistors and the gate electrode of the second transistors are connected in common.

16. The semiconductor memory device according to claim 1, wherein the second voltage is larger than the first voltage.

7. A semiconductor memory device comprising:

a memory cell array in which a plurality of memory cells are arranged in a matrix;

a plurality of word lines connected to the plurality of memory cells;

a plurality of bit lines connected to each of one end of the memory cells; and

a control circuit configured to control the potentials of said plurality of word lines and said plurality of bit lines,

wherein the control circuit sets a first voltage to first word lines of k (k is a natural number) of the plurality of word lines in an erase operation, sets a second voltage (the first voltage <

the second voltage) to second word lines of h (h is a natural number) of the plurality of word lines, sets a third voltage (the third voltage <

the first voltage) to a third word lines of n (n is a natural number) of the plurality of word lines, and carries out the erase operation.

8. The semiconductor memory device according to claim 7, wherein the first word lines are adjacent to the third word lines, and the third word lines are adjacent to the second word lines.

9. The semiconductor memory device according to claim 7, wherein the memory cells constitute a plurality of blocks as an erase unit, and

wherein the memory cells in the blocks are series-connected and constitute a series circuit, the second word lines are connected to the memory cells arranged at both ends of the series circuit, the third word lines are connected to the memory cells adjacent to the memory cells which are connected to the second word lines, and the first word lines are connected to another memory cells of the series circuit.

10. The semiconductor memory device according to claim 9, further comprising,

first transistors connected to each of the first word lines in the block, wherein a voltage which is step-upped is supplied to a gate electrode of the first transistors.

11. The semiconductor memory device according to claim 9, further comprising,

second transistors connected to each of the second word lines in the block, wherein a voltage which is step-upped is supplied to a gate electrode of the second transistors.

12. The semiconductor memory device according to claim 10, further comprising:

second transistors connected to each of the first word lines,

wherein the gate electrode of the first transistor and the gate electrode of the second transistor are connected in common.

13. The semiconductor memory device according to claim 11, further comprising:

first transistors connected to each of the first word lines in the block,

wherein the gate electrode of the first transistor and the gate electrode of the second transistor are connected in common.

14. A semiconductor memory device comprising:

a memory cell array in which a plurality of memory cells are arranged in a matrix;

a plurality of word lines connected to the plurality of memory cells;

a plurality of bit lines connected to each of one end of the memory cells; and

a control circuit configured to control the potentials of said plurality of word lines and said plurality of bit lines,

wherein the control circuit sets a first voltage to first word lines of k (k is a natural number) of the plurality of word lines in an erase operation, sets a second voltage (the first voltage <

the second voltage) to a second word lines of h (h is a natural number) of the plurality of word lines, and carries out the erase operation,

wherein the memory cells constitute a plurality of blocks as an erase unit, and

wherein the memory cells in the blocks are series-connected and which constitutes a series circuit, the second word lines are connected to the memory cells arranged at both ends of the series circuit, and the first word lines are connected to another memory cells of the series circuit.

15. The semiconductor memory device according to claim 14, wherein the first word lines are adjacent to the second word lines.