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Receiver equalizer circuitry with offset voltage compensation for use on integrated circuits

  • US 8,335,249 B1
  • Filed: 11/25/2009
  • Issued: 12/18/2012
  • Est. Priority Date: 11/25/2009
  • Status: Active Grant
First Claim
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1. Equalizer circuitry on an integrated circuit comprising:

  • first, second, and third continuous time, linear, equalizer stages connected in series with one another in order from the first stage through the second stage to the third stage, each of the equalizer stages including peaking inductor circuitry; and

    controllably variable, static, DC mode offset voltage compensation circuitry for controllably reducing DC voltage offset between an output signal of the third stage and utilization circuitry to which that output signal is applied;

    wherein;

    one of the equalizer stages includes a controllably variable current source; and

    the static, DC mode offset voltage compensation circuitry controls current of the current source, the static, DC mode offset voltage compensation circuitry comprising memory circuitry for loading with values to control the current of the current source.

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