Receiver equalizer circuitry with offset voltage compensation for use on integrated circuits

• US 8,335,249 B1
• Filed: 11/25/2009
• Issued: 12/18/2012
• Est. Priority Date: 11/25/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Su, Xiaoyan, Narayan, Sriram, Wong, Wilson, Shumarayev, Sergey
• Primary Examiner(s): Tran, Khanh C
• Application Number:
  US12/626,379
• Time in Patent Office: 1,119 Days
• Field of Search: 375229-230, 375/232, 375/350, 708322-323, 330/304
• US Class Current: 375/232
• CPC Class Codes: H03F 3/45197 Pl types H03F3/45224, H03F3/45251 take precedence
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

Equalizer circuitry on an integrated circuit (“IC”) includes first, second, and third continuous time, equalizer stages connected in series. Each stage includes peaking inductor circuitry. The equalizer circuitry may further include controllably variable, static, DC mode offset voltage compensation circuitry and/or dynamic, continuous mode, offset voltage compensation circuitry for respectively reducing DC voltage offset and/or time-varying, continuous mode voltage offset between an output of the third equalizer stage and utilization circuitry to which that output is applied. The first equalizer stage may be preceded by termination circuitry having controllably variable impedance. Differential circuitry and signalling may be used for various circuit components. The equalizer circuitry is particularly useful for fabrication as part of a programmable IC, using 28 nm CMOS technology, and as a receiver equalizer for a high-speed serial data signal having a bit rate of 20-25 Gbps.

Claims

1. Equalizer circuitry on an integrated circuit comprising:

first, second, and third continuous time, linear, equalizer stages connected in series with one another in order from the first stage through the second stage to the third stage, each of the equalizer stages including peaking inductor circuitry; and

controllably variable, static, DC mode offset voltage compensation circuitry for controllably reducing DC voltage offset between an output signal of the third stage and utilization circuitry to which that output signal is applied;

wherein;

one of the equalizer stages includes a controllably variable current source; and

the static, DC mode offset voltage compensation circuitry controls current of the current source, the static, DC mode offset voltage compensation circuitry comprising memory circuitry for loading with values to control the current of the current source.

2. The equalizer circuitry defined in claim 1 wherein:

the one of the equalizer stages is the second equalizer stage; and

the static, DC mode offset voltage compensation circuitry operates on the second equalizer stage.

3. The equalizer circuitry defined in claim 1 further comprising:

dynamic, continuous mode, offset voltage compensation circuitry for reducing continuous mode voltage offset of the output signal.

4. The equalizer circuitry defined in claim 3 wherein the dynamic, continuous mode, offset voltage compensation circuitry operates on the first equalizer stage.

5. The equalizer circuitry defined in claim 4 wherein the first equalizer stage includes a controllably variable current source, and wherein the dynamic, continuous mode, offset voltage compensation circuitry controls current of the current source.

6. The equalizer circuitry defined in claim 5 wherein the dynamic, continuous mode, offset voltage compensation circuitry comprises:

feedback loop circuitry from the output signal to the current source.

7. The equalizer circuitry defined in claim 6 wherein the feedback loop circuitry comprises:

error amplifier circuitry for amplifying a voltage offset error in the output signal; and

voltage-to-current conversion circuitry for converting a voltage offset error signal output by the error amplifier circuitry to a proportional current signal for use by the current source.

8. The equalizer circuitry defined in claim 1 further comprising:

controllably variable termination circuitry for controllably varying an impedance of an input signal to the first equalizer stage.

9. The equalizer circuitry defined in claim 8 wherein the controllably variable termination circuitry comprises:

controllably variable resistance circuitry.

10. The equalizer circuitry defined in claim 9 further comprising:

memory circuitry for controlling resistance of the controllably variable resistance circuitry.

11. The equalizer circuitry defined in claim 1 wherein the utilization circuitry comprises:

clock and data recovery circuitry.

12. The equalizer circuitry defined in claim 1 wherein at least one of the equalizer stages comprises:

controllably variable resistor or capacitor circuitry for providing a pole of controllably variable position in frequency response of that equalizer stage.

13. The equalizer circuitry defined in claim 12 further comprising:

memory circuitry for controlling resistance or capacitance of the controllably variable resistor or capacitor circuitry.

14. The equalizer circuitry defined in claim 1 wherein at least one of the equalizer stages comprises differential circuitry.

15. The equalizer circuitry defined in claim 1 wherein the static, DC mode offset voltage compensation circuitry comprises differential circuitry.

16. The equalizer circuitry defined in claim 1 wherein the integrated circuit is a complex programmable logic device.

17. The equalizer circuitry defined in claim 1 wherein the equalizer circuitry is adapted for processing a high-speed special data signal having a bit rate of 20-25 Gbps.

18. The equalizer circuitry defined in claim 1 wherein the integrated circuit is fabricated using 28 nm CMOS fabrication technology.

19. Equalizer circuitry on an integrated circuit comprising:

first, second, and third continuous time, linear, equalizer stages connected in series with one another in order from the first stage through the second stage to the third stage, each of the equalizer stages including peaking inductor circuitry; and

dynamic, continuous mode, offset voltage compensation circuitry for monitoring an output signal of the third stage and continuously reducing voltage offset between the output signal of the third stage and utilization circuitry to which that output signal is applied.

20. The equalizer circuitry defined in claim 19 wherein the dynamic, continuous mode, offset voltage compensation circuitry operates on the first equalizer stage.

21. The equalizer circuitry defined in claim 20 wherein the first equalizer stage includes a controllably variable current source, and wherein the dynamic, continuous mode, offset voltage compensation circuitry controls current of the current source.

22. The equalizer circuitry defined in claim 21 wherein the dynamic, continuous mode, offset voltage compensation circuitry comprises:

feedback loop circuitry from the output signal to the current source.

23. The equalizer circuitry defined in claim 22 wherein the feedback loop circuitry comprises:

error amplifier circuitry for amplifying a voltage offset error in the output signal; and

voltage-to-current conversion circuitry for converting a voltage offset error signal output by the error amplifier circuitry to a proportional current signal for use by the current source.

24. The equalizer circuitry defined in claim 19 further comprising:

controllably variable termination circuitry for controllably varying an impedance of an input signal to the first equalizer stage.

25. The equalizer circuitry defined in claim 24 wherein the controllably variable termination circuitry comprises:

controllably variable resistance circuitry.

26. The equalizer circuitry defined in claim 25 further comprising:

memory circuitry for controlling resistance of the controllably variable resistance circuitry.

27. The equalizer circuitry defined in claim 19 wherein the utilization circuitry comprises:

clock and data recovery circuitry.

28. The equalizer circuitry defined in claim 19 wherein at least one of the equalizer stages comprises:

controllably variable resistor or capacitor circuitry for providing a pole of controllably variable position in frequency response of that equalizer stage.

29. The equalizer circuitry defined in claim 28 further comprising:

memory circuitry for controlling resistance or capacitance of the controllably variable resistor or capacitor circuitry.

30. The equalizer circuitry defined in claim 19 wherein at least one of the equalizer stages comprises differential circuitry.

31. The equalizer circuitry defined in claim 19 wherein the dynamic, continuous mode, offset voltage compensation circuitry comprises differential circuitry.

32. Equalizer circuitry on an integrated circuit comprising:

first, second, and third continuous time, linear, differential, equalizer stages connected in series with one another in order from the first stage through the second stage to the third stage, each of the equalizer stages including peaking inductors; and

dynamic, continuous mode, differential, offset voltage compensation circuitry for monitoring differential output signals of the third stage and continuously reducing voltage offset between the differential output signals of the third stage and utilization circuitry to which those differential output signals are applied.