Systems and methods for dynamically controlling an analog-to-digital converter
First Claim
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1. A system for power conservation in a receiver device, comprising:
- a tuner;
a programmable analog-to-digital converter (ADC); and
a digital signal processing hardware (DSPHW) including logic executable by the DSPHW to;
configure the tuner to operate in a first mode,measure a first power of a desired signal and a first total power at an input of the ADC,determine a first ratio based at least in part on the first power of the desired signal and the first total power at the input of the ADC,configure the tuner to operate in a second mode,measure a second power of the desired signal and a second total power at the input of the ADC,determine a second ratio based at least in part on the second power of the desired signal and the second total power at the input of the ADC,configure the tuner to operate in the first mode or the second mode based at least in part on a comparison of the first ratio and the second ratio,measure a third power of the desired signal;
generate a control signal to configure components within the receiver device to conserve power at the ADC,calculate an available noise margin between the third power of the desired signal and a noise floor,calculate a resolution of the ADC based at least in part on the available noise margin, andconfigure the ADC with the calculated resolution.
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Abstract
Systems and methods for dynamically controlling an analog-to-digital converter (ADC) in order to conserve power are provided. In exemplary embodiments, a receiver device comprises a tuner configured to receive a signal, at least one programmable analog-to-digital converter (ADC), and a digital signal processing hardware comprising a control logic. The exemplary control logic is configured to generate a control signal to configure components within the receiver device to conserve power at the ADC.
91 Citations
19 Claims
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1. A system for power conservation in a receiver device, comprising:
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a tuner; a programmable analog-to-digital converter (ADC); and a digital signal processing hardware (DSPHW) including logic executable by the DSPHW to; configure the tuner to operate in a first mode, measure a first power of a desired signal and a first total power at an input of the ADC, determine a first ratio based at least in part on the first power of the desired signal and the first total power at the input of the ADC, configure the tuner to operate in a second mode, measure a second power of the desired signal and a second total power at the input of the ADC, determine a second ratio based at least in part on the second power of the desired signal and the second total power at the input of the ADC, configure the tuner to operate in the first mode or the second mode based at least in part on a comparison of the first ratio and the second ratio, measure a third power of the desired signal; generate a control signal to configure components within the receiver device to conserve power at the ADC, calculate an available noise margin between the third power of the desired signal and a noise floor, calculate a resolution of the ADC based at least in part on the available noise margin, and configure the ADC with the calculated resolution. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for power conservation in a receiver device, comprising:
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receiving a signal at the receiver device, the receiver device including a programmable analog-to-digital converter (ADC), a tuner, and an oscillator; measuring a first power of the signal and a first total power at an input of the ADC, determining a first ratio based at least in part on the first power of the signal and the first total power at the input of the ADC, configuring the tuner to operate in a second mode, measuring a second power of the signal and a second total power at the input of the ADC, determining a second ratio based at least in part on the second power of the signal and the second total power at the input of the ADC, configuring the tuner to operate in the first mode or the second mode based at least in part on a comparison of the first ratio and the second ratio, measuring a third power of the signal; calculating an available noise margin between the third power of the signal and a noise floor; calculating a resolution for the ADC based at least in part on the available noise margin; and dynamically adjusting the resolution by adjusting the frequency of the local oscillator sine wave such that an effective dynamic range of the ADC is minimized to conserve power at the ADC while allowing for reliable demodulation of the signal, the adjustment of the frequency of the oscillator being based at least in part on a power of a desired signal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification