Multi-processor architecture implementing a serial switch and method of operating same
First Claim
1. A multi-processor architecture comprising:
- a first plurality of processors that control the routing of packets;
a first PCI-Express (PCIe) switch, wherein each of the first plurality of processors is coupled to the first PCIe switch by a corresponding point-to-point serial link;
first packet processing logic coupled to the first PCIe switch by a point-to-point serial link, wherein all data packets transferred between the first packet processing logic and the first plurality of processors pass through the first PCIe switch, wherein the first plurality of processors, the first PCIe switch and the first packet processing logic are located on a first blade.
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Accused Products
Abstract
A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards.
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Citations
22 Claims
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1. A multi-processor architecture comprising:
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a first plurality of processors that control the routing of packets; a first PCI-Express (PCIe) switch, wherein each of the first plurality of processors is coupled to the first PCIe switch by a corresponding point-to-point serial link; first packet processing logic coupled to the first PCIe switch by a point-to-point serial link, wherein all data packets transferred between the first packet processing logic and the first plurality of processors pass through the first PCIe switch, wherein the first plurality of processors, the first PCIe switch and the first packet processing logic are located on a first blade. - View Dependent Claims (2)
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3. A multi-processor architecture comprising:
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a first plurality of processors that control the routing of packets; a first PCI-Express (PCIe) switch, wherein each of the first plurality of processors is coupled to the first PCIe switch by a point-to-point serial link; first packet processing logic coupled to the first PCIe switch by a point-to-point serial link, wherein data packets are transferred between the first packet processing logic and the first plurality of processors through the first PCIe switch; a second plurality of processors; a second PCIe switch, wherein each of the second plurality of processors is coupled to the second PCIe switch by a point-to-point serial link; and second packet processing logic coupled to the second PCIe switch by a point-to-point serial link, wherein packets are transferred between the second packet processing logic and the second plurality of processors through the second PCIe switch. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10)
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11. A method of implementing a multi-processor architecture comprising:
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receiving a first packet with a first blade that includes a first plurality of multi-core processors; routing the first packet to one of the first plurality of multi-core processors through a first PCI-Express (PCIe) switch on the first blade. - View Dependent Claims (12, 13)
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14. A method of implementing a multi-processor architecture comprising:
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receiving a first packet with a first blade that includes a first plurality of multi-core processors; routing the first packet to one of the first plurality of multi-core processors through a first PCI-Express (PCIe) switch on the first blade; receiving a second packet with a second blade that includes a second plurality of multi-core processors; and routing the second packet to one of the second plurality of multi-core processors through a second PCIe switch on the second blade. - View Dependent Claims (15)
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16. A multi-processor architecture comprising:
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a first plurality of processors, each having a PCI-Express (PCIe) interface; a first PCIe switch; a first set of point-to-point serial links that couple each PCIe interface of the first plurality of processors to the first PCIe switch; first packet processing logic having a PCIe interface; and a second set of point-to-point serial links that couple the PCIe interface of the first packet processing logic to the first PCIe switch, wherein the first plurality of processors, the first PCIe switch and the first packet processing logic are located on a first blade. - View Dependent Claims (17)
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18. A multi-processor architecture comprising:
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a first plurality of processors, each having a PCI-Express (PCIe) interface; a first PCIe switch; a first set of point-to-point serial links that couple each PCIe interface of the first plurality of processors to the first PCIe switch; first packet processing logic having a PCIe interface; a second set of point-to-point serial links that couple the PCIe interface of the first packet processing logic to the first PCIe switch; a second plurality of processors, each having a PCIe interface; a second PCIe switch; a third set of point-to-point serial links that couple each PCIe interface of the second plurality of processors to the second PCIe switch; second packet processing logic having a PCIe interface; and a fourth set of point-to-point serial links that couple the PCIe interface of the second packet processing logic to the second PCIe switch. - View Dependent Claims (19, 20, 21, 22)
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Specification