Multi-processor architecture implementing a serial switch and method of operating same

• US 8,335,884 B2
• Filed: 07/10/2009
• Issued: 12/18/2012
• Est. Priority Date: 07/10/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Inventors: Hamadani, Mehrdad, Bansal, Deepak, Moy, Sam Htin, Malli, Sreenivasulu, Cheung, David, Kancherla, Mani, Devarapalli, Sridhar
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US12/501,389
• Publication Number:
  US 20110010481A1
• Time in Patent Office: 1,257 Days
• Field of Search: 710300-317, 710 36- 42, 709238-239
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards.

Claims

1. A multi-processor architecture comprising:

a first plurality of processors that control the routing of packets;

a first PCI-Express (PCIe) switch, wherein each of the first plurality of processors is coupled to the first PCIe switch by a corresponding point-to-point serial link;

first packet processing logic coupled to the first PCIe switch by a point-to-point serial link, wherein all data packets transferred between the first packet processing logic and the first plurality of processors pass through the first PCIe switch, wherein the first plurality of processors, the first PCIe switch and the first packet processing logic are located on a first blade.

2. The multi-processor architecture of claim 1, wherein the first packet processing logic implements posted write direct memory access (DMA) operations to the first plurality of processors.

3. A multi-processor architecture comprising:

a first plurality of processors that control the routing of packets;

a first PCI-Express (PCIe) switch, wherein each of the first plurality of processors is coupled to the first PCIe switch by a point-to-point serial link;

first packet processing logic coupled to the first PCIe switch by a point-to-point serial link, wherein data packets are transferred between the first packet processing logic and the first plurality of processors through the first PCIe switch;

a second plurality of processors;

a second PCIe switch, wherein each of the second plurality of processors is coupled to the second PCIe switch by a point-to-point serial link; and

second packet processing logic coupled to the second PCIe switch by a point-to-point serial link, wherein packets are transferred between the second packet processing logic and the second plurality of processors through the second PCIe switch.

4. The multi-processor architecture of claim 3, further comprising a third PCIe switch coupling the first and second PCIe switches.

5. The multi-processor architecture of claim 3, wherein the first plurality of processors, the first PCIe switch and the first packet processing logic are located on a first blade, and the second plurality of processors, the second PCIe switch and the second packet processing logic are located on a second blade.

6. The multi-processor architecture of claim 4, further comprising a first management processor coupled to the third PCIe switch.

7. The multi-processor architecture of claim 4, further comprising a fourth PCIe switch coupled to the third PCIe switch.

8. The multi-processor architecture of claim 6, further comprising a first processor accelerator coupled to the third PCIe switch.

9. The multi-processor architecture of claim 8, further comprising:

a second management processor coupled to the third PCIe switch; and

a second processor accelerator coupled to the third PCIe switch.

10. The multi-processor architecture of claim 7, further comprising:

one or more line cards that transmit and receive packets; and

a switch fabric that couples each of the one or more line cards to the first packet processing logic and the second packet processing logic, wherein the fourth PCIe switch is coupled to each of the one or more line cards and the switch fabric.

11. A method of implementing a multi-processor architecture comprising:

receiving a first packet with a first blade that includes a first plurality of multi-core processors;

routing the first packet to one of the first plurality of multi-core processors through a first PCI-Express (PCIe) switch on the first blade.

12. The method of claim 11, further comprising routing the first packet through the first PCIe switch on a plurality of point-to-point serial links.

13. The method of claim 11, further comprising implementing a posted write direct memory access (DMA) process when routing the first packet to one of the first plurality of multi core processors.

14. A method of implementing a multi-processor architecture comprising:

receiving a first packet with a first blade that includes a first plurality of multi-core processors;

routing the first packet to one of the first plurality of multi-core processors through a first PCI-Express (PCIe) switch on the first blade;

receiving a second packet with a second blade that includes a second plurality of multi-core processors; and

routing the second packet to one of the second plurality of multi-core processors through a second PCIe switch on the second blade.

15. The method of claim 14, further comprising:

routing the first packet through a switch fabric to the first blade; and

routing the second packet through the switch fabric to the second blade.

16. A multi-processor architecture comprising:

a first plurality of processors, each having a PCI-Express (PCIe) interface;

a first PCIe switch;

a first set of point-to-point serial links that couple each PCIe interface of the first plurality of processors to the first PCIe switch;

first packet processing logic having a PCIe interface; and

a second set of point-to-point serial links that couple the PCIe interface of the first packet processing logic to the first PCIe switch, wherein the first plurality of processors, the first PCIe switch and the first packet processing logic are located on a first blade.

17. The multi-processor architecture of claim 16, wherein the first set of point-to-point serial links include a plurality of point-to-point serial links connected between the PCIe interface of each of the first plurality of processors and the PCIe switch.

18. A multi-processor architecture comprising:

a first plurality of processors, each having a PCI-Express (PCIe) interface;

a first PCIe switch;

a first set of point-to-point serial links that couple each PCIe interface of the first plurality of processors to the first PCIe switch;

first packet processing logic having a PCIe interface;

a second set of point-to-point serial links that couple the PCIe interface of the first packet processing logic to the first PCIe switch;

a second plurality of processors, each having a PCIe interface;

a second PCIe switch;

a third set of point-to-point serial links that couple each PCIe interface of the second plurality of processors to the second PCIe switch;

second packet processing logic having a PCIe interface; and

a fourth set of point-to-point serial links that couple the PCIe interface of the second packet processing logic to the second PCIe switch.

19. The multi-processor architecture of claim 18, further comprising a third PCIe switch coupling the first and second PCIe switches.

20. The multi-processor architecture of claim 18, further comprising:

one or more line cards that transmit and receive packets; and

a switch fabric that couples each of the one or more line cards to the first packet processing logic and the second packet processing logic.

21. The multi-processor architecture of claim 18, wherein the first plurality of processors, the first PCIe switch and the first packet processing logic are located on a first blade, and the second plurality of processors, the second PCIe switch and the second packet processing logic are located on a second blade.

22. The multi-processor architecture of claim 19, further comprising a first management processor coupled to the third PCIe switch.