Configurable memory system with interface circuit
First Claim
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1. A memory module comprising:
- a first rank of memory circuits comprising a first memory circuit;
a second rank of memory circuits comprising a second memory circuit;
an interface circuit;
a first data bus that connects to the first memory circuit, the second memory circuit, and the interface circuit, the first data bus having a first data bus width; and
a second data bus that connects to the interface circuit and a memory controller, the second data bus having a second data bus width, wherein the second data bus width is half of the first data bus width;
wherein the interface circuit is operable to;
receive a read command from the memory controller to read data that is stored in the memory module, wherein the data associated with the read command includes first data stored in the first memory circuit and second data stored in the second memory circuit;
enable a chip select pin of the first memory circuit to connect the first memory circuit to the first data bus;
read the first data from the first memory circuit across the first data bus;
transmit the first data to the memory controller across the second data bus;
insert idle clock cycles, and during the idle clock cycles;
(i) disable the chip select pin of the first memory circuit to disconnect the first memory circuit from the first data bus, and(ii) enable a chip select pin of the second memory circuit to connect the second memory circuit to the first data bus, while the first data is being transmitted to the memory controller across the second data bus;
read the second data from the second memory circuit across the first data bus; and
transmit the second data to the memory controller across the second data bus without a delay on the second data bus between the first data and the second data.
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Abstract
An interface circuit that emulates a memory circuit having a first organization using a memory circuit having a second organization, wherein the second organization includes a number of banks, a number of rows, a number of columns, and a number of bits per column.
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Citations
24 Claims
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1. A memory module comprising:
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a first rank of memory circuits comprising a first memory circuit; a second rank of memory circuits comprising a second memory circuit; an interface circuit; a first data bus that connects to the first memory circuit, the second memory circuit, and the interface circuit, the first data bus having a first data bus width; and a second data bus that connects to the interface circuit and a memory controller, the second data bus having a second data bus width, wherein the second data bus width is half of the first data bus width; wherein the interface circuit is operable to; receive a read command from the memory controller to read data that is stored in the memory module, wherein the data associated with the read command includes first data stored in the first memory circuit and second data stored in the second memory circuit; enable a chip select pin of the first memory circuit to connect the first memory circuit to the first data bus; read the first data from the first memory circuit across the first data bus; transmit the first data to the memory controller across the second data bus; insert idle clock cycles, and during the idle clock cycles; (i) disable the chip select pin of the first memory circuit to disconnect the first memory circuit from the first data bus, and (ii) enable a chip select pin of the second memory circuit to connect the second memory circuit to the first data bus, while the first data is being transmitted to the memory controller across the second data bus; read the second data from the second memory circuit across the first data bus; and transmit the second data to the memory controller across the second data bus without a delay on the second data bus between the first data and the second data. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory module comprising:
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a first rank of memory circuits comprising a first memory circuit; a second rank of memory circuits comprising a second memory circuit; an interface circuit; a first data bus that connects to the first memory circuit and the interface circuit, the first data bus having a first data bus width; a second data bus that connects to the second memory circuit and the interface circuit, the second data bus having the first data bus width; and a third data bus that connects to a memory controller and the interface circuit, the third data bus having a second data bus width, wherein the second data bus width is twice of the first data bus width; wherein the interface circuit is operable to; receive a read command from the memory controller to read data that is stored in the memory module, wherein the data associated with the read command includes first data stored in the first memory circuit and second data stored in the second memory circuit; read the first data from the first memory circuit across the first data bus; transmit the first data to the memory controller across the third data bus; while the first data is being transmitted to the memory controller across the third data bus, read the second data from the second memory circuit across the second data bus; and transmit the second data to the memory controller across the third data bus without a delay on the third data bus between the first data and the second data. - View Dependent Claims (8, 9, 10, 11)
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12. A memory subsystem comprising:
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an interface circuit; a first memory module comprising; a first rank of memory circuits comprising a first memory circuit; a second memory module comprising; a second rank of memory circuits comprising a second memory circuit; a first data bus that connects to the first memory circuit, the second memory circuit, and the interface circuit, the first data bus having a first data bus width; and a second data bus that connects to the interface circuit and a memory controller, the second data bus having a second data bus width, wherein the second data bus width is half of the first data bus width; wherein the interface circuit is operable to; receive a first read command from the memory controller to read data that is stored in the memory subsystem, wherein the data associated with the first read command includes first data stored in the first memory circuit and second data stored in the second memory circuit; enable a chip select pin of the first memory circuit to connect the first memory circuit to the first data bus; read the first data from the first memory circuit across the first data bus; transmit the first data to the memory controller across the second data bus; insert idle clock cycles, and during the idle clock cycles; (i) disable the chip select pin of the first memory circuit to disconnect the first memory circuit from the first data bus, and (ii) enable a chip select pin of the second memory circuit to connect the second memory circuit to the first data bus, while the first data is being transmitted to the memory controller across the second data bus; read the second data from the second memory circuit across the first data bus; and transmit the second data to the memory controller across the second data bus without a delay on the second data bus between the first data and the second data. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. A system comprising:
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a memory controller; an interface circuit; a first data bus having a first data bus width; a second data bus having a second data bus width, wherein the second data bus width is half of the first data bus width; and a memory module comprising; a first rank of memory circuits comprising a first memory circuit; and a second rank of memory circuits comprising a second memory circuit; wherein the first data bus connects to the first memory circuit, the second memory circuit, and the interface circuit; wherein the second data bus connects to the interface circuit and the memory controller; and wherein the interface circuit is operable to; receive a read command from the memory controller to read data that is stored in the memory module, wherein the data associated with the read command includes first data stored in the first memory circuit and second data stored in the second memory circuit; enable a chip select pin of the first memory circuit to connect the first memory circuit to the first data bus; read the first data from the first memory circuit across the first data bus; transmit the first data to the memory controller across the second data bus; insert idle clock cycles, and during the idle clock cycles; (i) disable the chip select pin of the first memory circuit to disconnect the first memory circuit from the first data bus, and (ii) enable a chip select pin of the second memory circuit to connect to the second memory circuit to the first data bus, while the first data is being transmitted to the memory controller across the second data bus; read the second data from the second memory circuit across the first data bus; and transmit the second data to the memory controller across the second data bus without a delay on the second data bus between the first data and the second data. - View Dependent Claims (22, 23, 24)
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Specification