Eliminating, coalescing, or bypassing ports in memory array representations
First Claim
1. A method, in a data processing system, for minimizing memory array representations, the method comprising:
- receiving, in the data processing system, an integrated circuit design having a memory array;
reducing, by the data processing system, a number of ports in the memory array in the integrated circuit design to form a reduced integrated circuit design; and
performing, by the data processing system, synthesis or verification on the reduced integrated circuit design,wherein reducing the number of ports in the memory array comprises;
responsive to a determination that the memory array is a write-before-read array, identifying a read port and a write port wherein the write port address matches the read port and every time the read port is enabled, the write port is also enabled; and
for each connected write pin, merging a corresponding read pin onto the connected write pin.
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Accused Products
Abstract
Mechanisms are provided in a design environment for eliminating, coalescing, or bypassing ports. The design environment comprises one mechanism to eliminate unnecessary ports in arrays using disabled and disconnected pin information. The design environment may comprise another mechanism to combine and reduce the number of array ports using address comparisons. The design environment may comprise another mechanism to combine and reduce the number of array ports using disjoint enable comparisons. The design environment may comprise one mechanism to combine and reduce the number of array ports using “don'"'"'t care” computations. The design environment may comprise another mechanism to reduce the number of array ports through bypassing write-to-read paths around arrays.
74 Citations
23 Claims
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1. A method, in a data processing system, for minimizing memory array representations, the method comprising:
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receiving, in the data processing system, an integrated circuit design having a memory array; reducing, by the data processing system, a number of ports in the memory array in the integrated circuit design to form a reduced integrated circuit design; and performing, by the data processing system, synthesis or verification on the reduced integrated circuit design, wherein reducing the number of ports in the memory array comprises; responsive to a determination that the memory array is a write-before-read array, identifying a read port and a write port wherein the write port address matches the read port and every time the read port is enabled, the write port is also enabled; and for each connected write pin, merging a corresponding read pin onto the connected write pin. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A computer program product comprising a non-transitory computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:
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receive, in the computing device, an integrated circuit design having a memory array; reduce, by the computing device, a number of ports in the memory array in the integrated circuit design to form a reduced integrated circuit design; and perform, by the computing device, synthesis or verification on the reduced integrated circuit design, wherein reducing the number of ports in the memory array comprises; responsive to a determination that the memory array is a write-before-read array, identifying a read port and a write port, wherein the write port address matches the read port and every time the read port is enabled, the write port is also enabled; and for each connected write pin, merging a corresponding read pin onto the connected write pin. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. An apparatus, comprising:
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a processor; and a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to; receive an integrated circuit design having a memory array; reduce a number of ports in the memory array in the integrated circuit design to form a reduced integrated circuit design; and perform synthesis or verification on the reduced integrated circuit design, wherein reducing the number of ports in the memory array comprises; responsive to a determination that the memory array is a write-before-read array, identifying a read port and a write port, wherein the write port address matches the read port and every time the read port is enabled, the writeport is also enabled; and for each connected write pin, a corresponding read pin onto the connected write pin. - View Dependent Claims (22, 23)
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Specification