Package process of stacked type semiconductor device package structure

• US 8,338,235 B2
• Filed: 04/23/2010
• Issued: 12/25/2012
• Est. Priority Date: 02/11/2010
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Wang, Meng-Jen
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): HENRY, CALEB E
• Application Number:
  US12/766,549
• Publication Number:
  US 20110195545A1
• Time in Patent Office: 977 Days
• Field of Search: 257/723, 257/700, 438/113, 438107-109, 438/112
• US Class Current: 438/113
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

Abstract

A package process is provided. The package process includes: disposing a semiconductor substrate on a carrier, wherein the semiconductor substrate has plural contacts at a side facing the carrier; thinning the semiconductor substrate from a back side of the semiconductor substrate and then forming plural through silicon vias in the thinned semiconductor substrate; forming plural first pads on the semiconductor substrate, wherein the first pads respectively connected to the through silicon vias; bonding plural chips to the semiconductor substrate, wherein the chips are electrically connected to the corresponding pads; forming a molding compound on the semiconductor substrate to cover the chips and the first pads; separating the semiconductor substrate and the carrier and then forming plural solder balls on the semiconductor substrate; and sawing the molding compound and the semiconductor substrate.

Claims

1. A package process, comprising:

disposing a semiconductor substrate on a carrier, wherein the semiconductor substrate has a first surface facing the carrier and plural contacts on the first surface, and the semiconductor substrate is bonded to the carrier with a passivation layer on the first surface;

thinning the semiconductor substrate from a back side of the semiconductor substrate in opposite to the first surface, wherein the thinned semiconductor substrate has a second surface opposite to the first surface;

forming plural through silicon vias in the thinned semiconductor substrate, wherein the through silicon vias respectively correspond to and connect to the contacts;

forming plural first pads on the second surface of the semiconductor substrate, wherein the first pads respectively correspond to and connect to the through silicon vias;

bonding plural chips to the second surface of the semiconductor substrate, wherein the chips respectively electrically connect to the corresponding first pads;

forming a molding compound on the second surface of the semiconductor substrate, wherein the molding compound covers the chips and the first pads;

separating the semiconductor substrate and the carrier, wherein the passivation layer is remained on the first surface of the semiconductor substrate;

forming a redistribution layer on the passivation layer after the semiconductor substrate and the carrier are separated, wherein a surface of the redistribution layer has plural second pads, and the second pads respectively electrically connect to the contacts;

forming plural solder balls on the first surface of the semiconductor substrate, wherein the solder balls respectively electrically connect to the corresponding contacts; and

simultaneously sawing the molding compound and the semiconductor substrate to form a plurality of package units.

2. The package process according to claim 1, further comprising:

forming an under bump metallurgy layer on each of the second pads.

3. The package process according to claim 1, further comprising:

forming an under bump metallurgy layer on each of the first pads.

4. The package process as claimed in claim 1, wherein the step of bonding the chips to the second surface of the semiconductor substrate includes bonding each of the chips to the corresponding first pads through plural conductive bumps by a flip chip bonding technique.

5. The package process according to claim 4, further comprising:

forming an underfill between each of the chips and the semiconductor substrate after the chips are bonded to the second surface of the semiconductor substrate and before the molding compound is formed on the second surface of the semiconductor substrate, wherein the underfill encapsulates the conductive bumps.

6. The package process as claimed in claim 2, further comprising:

forming a solder ball on each of the under bump metallurgy layer.

7. The package process as claimed in claim 1, wherein the molding compound directly fill in a gap between the chips and the semiconductor substrate.

8. The package process according to claim 1, further comprising:

forming an under bump metallurgy layer on each of the first pads.