Integrated circuit system employing stress-engineered spacers

• US 8,338,245 B2
• Filed: 03/14/2008
• Issued: 12/25/2012
• Est. Priority Date: 12/14/2006
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation, Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.)), Samsung Electronics Co. Ltd.
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.), International Business Machines Corporation, Samsung Electronics Co. Ltd.
• Inventors: Lee, Jae Gon, Yang, Jong Ho, Chan, Victor, Kim, Jun Jung
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Nicely, Joseph C
• Application Number:
  US12/048,994
• Publication Number:
  US 20080173934A1
• Time in Patent Office: 1,747 Days
• Field of Search: 438/199, 438/200, 438/210, 438/238, 438/382, 438/384, 438/595, 438/519, 438/521, 257/E21.004, 257/E21.626, 257/E21.64
• US Class Current: 438/210
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.

Claims

1. A method for manufacturing an integrated circuit system comprising:

providing a substrate including a first region with a first device and a second device and a second region with a resistor device;

configuring each of the first device, the second device, and the resistor device to include a gate, a gate dielectric, a first spacer and a second spacer;

forming a stress inducing layer over the first region and the second region;

processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and

forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer, the stress inducing layer including a portion remaining over the second region with a stress altered boundary between the second device and the resistor device.

2. The method as claimed in claim 1 wherein:

providing the first device includes providing an NFET device and providing the second device includes providing a PFET device.

3. The method as claimed in claim 1 wherein:

forming the stress inducing layer includes forming a tensile stressed layer.

4. The method as claimed in claim 1 wherein:

processing at least a portion of the stress inducing layer includes implanting germanium or xenon.

5. The method as claimed in claim 1 wherein:

forming the third spacer creates a first stress level in the first device and a second stress level in the second device, the first stress level differing from the second stress level.

6. A method for manufacturing an integrated circuit system comprising:

providing a substrate including a first region with a first device and a second device and a second region with a resistor device;

configuring each of the first device, the second device, and the resistor device to include a gate, a gate dielectric, a first spacer and a second spacer;

forming a stress inducing layer over the first region and the second region;

processing at least a portion of the stress inducing layer formed over the second device to alter the stress within the stress inducing layer; and

forming a third spacer from the stress inducing layer to create a first stress level in the first device and a second stress level in the second device, the first stress level differing from the second stress level and a portion of the stress inducing layer remaining over the second region with a stress altered boundary between the second device and the resistor device.

7. The method as claimed in claim 6 wherein:

forming the third spacer to create the first stress level within the first device includes adjusting the thickness of the third spacer adjacent the first device.

8. The method as claimed in claim 6 wherein:

forming the third spacer to create the second stress level within the second device includes adjusting the thickness of the third spacer adjacent the second device.

9. The method as claimed in claim 6 further comprising:

configuring the second device to include a punch-through suppression layer within a second device source/drain.

10. The method as claimed in claim 6 further comprising:

forming an electrical contact adjacent the third spacer of the first device and the second device.