Semiconductor memory device and method for manufacturing same

• US 8,338,882 B2
• Filed: 07/22/2010
• Issued: 12/25/2012
• Est. Priority Date: 03/10/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Hiroyasu, Katsumata, Ryota, Kito, Masaru, Fukuzumi, Yoshiaki, Aochi, Hideaki
• Primary Examiner(s): TRAN, LONG K
• Application Number:
  US12/841,662
• Publication Number:
  US 20110220987A1
• Time in Patent Office: 887 Days
• Field of Search: 257/324, 257/326, 257/329, 365/185.17
• US Class Current: 257/324
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.

Claims

1. A semiconductor memory device comprising:

a base including a substrate and a peripheral circuit formed on a surface of the substrate;

a stacked body including a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base;

a memory film provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers and including a charge storage film;

a channel body provided on an inside of the memory film in the memory hole;

an interconnection provided below the stacked body, and electrically connecting the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region, wherein the memory cell array region having the memory film and the channel body and the peripheral circuit; and

a contact plug piercing the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region; and

wherein the channel body is formed in a U-shaped configuration including;

a pair of columns extending in a stack direction of the stacked body; and

a connection buried in the lowermost layer of the conductive layers in the memory cell array region and connecting the pair of columns.

2. The device according to claim 1, wherein the lowermost layer of the conductive layers in the interconnection region connected to the contact plug and the interconnection, and the lowermost layer of the conductive layers in the memory cell array region are divided by an interlayer insulating film interposed between the lowermost layer of the conductive layers in the interconnection region and the lowermost layer of the conductive layers in the memory cell array region.

3. The device according to claim 1, further comprising a layer provided above the base, stacked on the lowermost of the conductive layers below the lowermost layer of conductive layers, and containing a metal.

4. The device according to claim 3, wherein

the lowermost layer of the conductive layers is a silicon layer and

the layer containing a metal is a metal silicide layer.

5. The device according to claim 3, wherein the contact plug pierces the lowermost layer of conductive layers in the interconnection region to reach the layer containing a metal.

6. The device according to claim 1, further comprising an insulator provided between the contact plug and the stacked body in the interconnection region.

7. The device according to claim 1, further comprising a bit line connected to the channel body above the stacked body,

the contact plug being connected to the bit line above the stacked body.

8. The device according to claim 1, wherein part of the stacked body on an outside of the memory cell array region is processed into a staircase shape.

9. The device according to claim 8, further comprising:

an interlayer insulating film provided above the portion processed into a staircase shape; and

a plurality of contact plugs piercing the interlayer insulating film to reach the respective conductive layers of corresponding stairs.

10. The device according to claim 1, wherein conductive layers other than the lowermost layer of the conductive layers in the stacked body in the interconnection region are dummy layers not electrically connected to other conductive portions.

11. A semiconductor memory device comprising:

a base including a substrate and a peripheral circuit formed on a surface of the substrate;

a stacked body including a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base;

a memory film provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers and including a charge storage film;

a channel body provided on an inside of the memory film in the memory hole;

an interconnection provided below the stacked body, and electrically connecting the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region, wherein the memory cell array region having the memory film and the channel body and the peripheral circuit;

a contact plug piercing the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region; and

wherein the lowermost layer of the conductive layers in the interconnection region connected to the contact plug and the interconnection is formed as a pad having a larger planar size than a line width of the interconnection.