Buried gate transistor
First Claim
1. A buried gate transistor device comprising:
- a semiconductor body including an active region, the active region surrounded by an isolation region;
a recess disposed in the active region;
a dielectric layer lining sidewalls and a bottom surface of the recess;
a gate electrode conductor filling the recess such that the dielectric layer is disposed between the gate electrode conductor and semiconductor material of the active region;
a first source/drain region disposed within the active region adjacent at least an upper portion of a first sidewall of the recess, the first source/drain region being heavily doped to a first conductivity type, wherein the first source/drain region abuts the dielectric layer at a point on the sidewall, wherein the dielectric layer is thinner at the point than on the bottom surface of the recess;
a second source/drain region disposed within the active region adjacent at least an upper portion of a second sidewall of the recess, the second source/drain region being heavily doped to the first conductivity type, the second source/drain region being spaced from the first source/drain region by the recess, wherein the second source/drain region abuts the dielectric layer at a point on the sidewall, wherein the dielectric layer is thinner at the point than on the bottom surface of the recess, wherein an upper portion of the gate electrode conductor extends above an upper surface of the first and second source/drain regions;
a spacer region disposed on a first part of sidewalls of the upper portion of the gate electrode conductor, a bottom surface of the spacer region being disposed over the first and second source/drain regions;
a first insulating layer disposed between the spacer region and the first source/drain region, a sidewall of the first insulating layer disposed on a second part of the sidewalls of the upper portion of the gate electrode conductor;
a second insulating layer disposed between the spacer region and the second source/drain region, a sidewall of the second insulating layer disposed on a third part of the sidewalls of the upper portion of the gate electrode conductor;
a silicide region disposed on a portion of the upper surface of the first active region, the silicide region being laterally separated from the gate electrode conductor by the spacer region; and
a channel region disposed within the active region at least beneath the bottom surface of the recess, the channel region being lightly doped to a second conductivity type that is opposite the first conductivity type, wherein the recess, the dielectric layer lining the sidewalls and the bottom surface of the recess, and the gate electrode conductor filling the recess extend into an adjacent active region.
2 Assignments
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Accused Products
Abstract
An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.
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Citations
16 Claims
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1. A buried gate transistor device comprising:
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a semiconductor body including an active region, the active region surrounded by an isolation region; a recess disposed in the active region; a dielectric layer lining sidewalls and a bottom surface of the recess; a gate electrode conductor filling the recess such that the dielectric layer is disposed between the gate electrode conductor and semiconductor material of the active region; a first source/drain region disposed within the active region adjacent at least an upper portion of a first sidewall of the recess, the first source/drain region being heavily doped to a first conductivity type, wherein the first source/drain region abuts the dielectric layer at a point on the sidewall, wherein the dielectric layer is thinner at the point than on the bottom surface of the recess; a second source/drain region disposed within the active region adjacent at least an upper portion of a second sidewall of the recess, the second source/drain region being heavily doped to the first conductivity type, the second source/drain region being spaced from the first source/drain region by the recess, wherein the second source/drain region abuts the dielectric layer at a point on the sidewall, wherein the dielectric layer is thinner at the point than on the bottom surface of the recess, wherein an upper portion of the gate electrode conductor extends above an upper surface of the first and second source/drain regions; a spacer region disposed on a first part of sidewalls of the upper portion of the gate electrode conductor, a bottom surface of the spacer region being disposed over the first and second source/drain regions; a first insulating layer disposed between the spacer region and the first source/drain region, a sidewall of the first insulating layer disposed on a second part of the sidewalls of the upper portion of the gate electrode conductor; a second insulating layer disposed between the spacer region and the second source/drain region, a sidewall of the second insulating layer disposed on a third part of the sidewalls of the upper portion of the gate electrode conductor; a silicide region disposed on a portion of the upper surface of the first active region, the silicide region being laterally separated from the gate electrode conductor by the spacer region; and a channel region disposed within the active region at least beneath the bottom surface of the recess, the channel region being lightly doped to a second conductivity type that is opposite the first conductivity type, wherein the recess, the dielectric layer lining the sidewalls and the bottom surface of the recess, and the gate electrode conductor filling the recess extend into an adjacent active region. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A buried gate transistor device comprising:
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an active area of semiconductor material, the active area having an upper surface; a first source/drain region disposed in the active area; a second source/drain region disposed in the active area; a gate electrode disposed between the first source/drain region and the second source/drain region, a first portion of the gate electrode recessed within the semiconductor material of the active area and a second portion of the gate electrode extending beyond the upper surface of the active area, the gate electrode having lower and upper sidewalls; a channel region within the active area beneath the gate electrode and along a portion of the lower sidewalls, wherein the first and second source/drain regions meet the channel region at a region of the lower sidewalls; a gate dielectric disposed between the gate electrode and the semiconductor material of the active area, wherein the gate dielectric is thinner at the region where the first and second source/drain regions meet the channel than in other regions of the channel; a first insulating layer disposed on a top surface of the first source/drain region, a sidewall of the first insulating layer disposed on a first part of the upper sidewalls of the gate electrode; first and second sidewall spacers disposed along the upper sidewalls of the gate electrode, the first sidewall spacer being disposed on the first insulating layer; and silicide regions formed in the first and second source/drain regions, the silicide regions being laterally spaced from the gate electrode by the first and second sidewall spacers. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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Specification