Buried gate transistor

• US 8,338,887 B2
• Filed: 07/06/2005
• Issued: 12/25/2012
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Lindsay, Richard, Hierlemann, Matthias
• Primary Examiner(s): Kraig, William F
• Application Number:
  US11/175,835
• Publication Number:
  US 20070007571A1
• Time in Patent Office: 2,729 Days
• Field of Search: 257330-334, 257/622, 257/E29.26, 257/E21.384, 257/E21.419, 257/E21.428, 438/199, 438/259, 438/270
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 : with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Claims

1. A buried gate transistor device comprising:

a semiconductor body including an active region, the active region surrounded by an isolation region;

a recess disposed in the active region;

a dielectric layer lining sidewalls and a bottom surface of the recess;

a gate electrode conductor filling the recess such that the dielectric layer is disposed between the gate electrode conductor and semiconductor material of the active region;

a first source/drain region disposed within the active region adjacent at least an upper portion of a first sidewall of the recess, the first source/drain region being heavily doped to a first conductivity type, wherein the first source/drain region abuts the dielectric layer at a point on the sidewall, wherein the dielectric layer is thinner at the point than on the bottom surface of the recess;

a second source/drain region disposed within the active region adjacent at least an upper portion of a second sidewall of the recess, the second source/drain region being heavily doped to the first conductivity type, the second source/drain region being spaced from the first source/drain region by the recess, wherein the second source/drain region abuts the dielectric layer at a point on the sidewall, wherein the dielectric layer is thinner at the point than on the bottom surface of the recess, wherein an upper portion of the gate electrode conductor extends above an upper surface of the first and second source/drain regions;

a spacer region disposed on a first part of sidewalls of the upper portion of the gate electrode conductor, a bottom surface of the spacer region being disposed over the first and second source/drain regions;

a first insulating layer disposed between the spacer region and the first source/drain region, a sidewall of the first insulating layer disposed on a second part of the sidewalls of the upper portion of the gate electrode conductor;

a second insulating layer disposed between the spacer region and the second source/drain region, a sidewall of the second insulating layer disposed on a third part of the sidewalls of the upper portion of the gate electrode conductor;

a silicide region disposed on a portion of the upper surface of the first active region, the silicide region being laterally separated from the gate electrode conductor by the spacer region; and

a channel region disposed within the active region at least beneath the bottom surface of the recess, the channel region being lightly doped to a second conductivity type that is opposite the first conductivity type, wherein the recess, the dielectric layer lining the sidewalls and the bottom surface of the recess, and the gate electrode conductor filling the recess extend into an adjacent active region.

2. The device of claim 1, wherein the recess extends through portions of the isolation region adjacent the active region.

3. The device of claim 1, wherein the dielectric layer has a substantially uniform thickness along the bottom surface of the recess.

4. The device of claim 1, wherein the dielectric layer comprises a high dielectric constant material.

5. The device of claim 1, further comprising a halo region in the active region adjacent the channel region.

6. The device of claim 1, further comprising:

a first epitaxial semiconductor region above the first source/drain region; and

a second epitaxial semiconductor region above the second source/drain region.

7. The device of claim 1, wherein the silicide region comprises:

a first silicide region above the first source/drain region; and

a second silicide region above the second source/drain region.

8. A buried gate transistor device comprising:

an active area of semiconductor material, the active area having an upper surface;

a first source/drain region disposed in the active area;

a second source/drain region disposed in the active area;

a gate electrode disposed between the first source/drain region and the second source/drain region, a first portion of the gate electrode recessed within the semiconductor material of the active area and a second portion of the gate electrode extending beyond the upper surface of the active area, the gate electrode having lower and upper sidewalls;

a channel region within the active area beneath the gate electrode and along a portion of the lower sidewalls, wherein the first and second source/drain regions meet the channel region at a region of the lower sidewalls;

a gate dielectric disposed between the gate electrode and the semiconductor material of the active area, wherein the gate dielectric is thinner at the region where the first and second source/drain regions meet the channel than in other regions of the channel;

a first insulating layer disposed on a top surface of the first source/drain region, a sidewall of the first insulating layer disposed on a first part of the upper sidewalls of the gate electrode;

first and second sidewall spacers disposed along the upper sidewalls of the gate electrode, the first sidewall spacer being disposed on the first insulating layer; and

silicide regions formed in the first and second source/drain regions, the silicide regions being laterally spaced from the gate electrode by the first and second sidewall spacers.

9. The device of claim 8, wherein the silicide regions comprise cobalt silicide regions.

10. The device of claim 8, wherein the gate electrode comprises a semiconductor material, the device further comprising a silicide region along an upper portion of the gate electrode.

11. The device of claim 8, wherein the active area is surrounded by an isolation region, the gate electrode extending through a trench in the isolation region.

12. The device of claim 8, further comprising a halo region in the active area adjacent a lower portion of the gate electrode.

13. The device of claim 8, wherein the first and second source/drain regions comprise epitaxially-grown semiconductor regions.

14. The device of claim 8, further comprising another active region separated from the active region by a trench isolation region, wherein a recessed first portion of the gate electrode extends from the active region across the trench isolation region to the another active region.

15. The device of claim 8, further comprising a second insulating layer disposed on a top surface of the second source/drain region, a sidewall of the second insulating layer disposed on a second part of the sidewalls of the gate electrode, wherein the second sidewall spacer is disposed on the second insulating layer.

16. The device of claim 15, wherein the first and second insulating layers comprise an oxide, and wherein the first and second sidewall spacers comprise a nitride.