TSV formation processes using TSV-last approach

• US 8,338,939 B2
• Filed: 07/12/2010
• Issued: 12/25/2012
• Est. Priority Date: 07/12/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jing-Cheng, Yang, Ku-Feng, Lin, Yung-Chi
• Primary Examiner(s): Vu, David
• Application Number:
  US12/834,304
• Publication Number:
  US 20120007154A1
• Time in Patent Office: 897 Days
• Field of Search: 438/55, 438/106, 438/107, 438/113, 438/124, 438/125, 438/126, 438/127, 257/737, 257/784, 257/E21.499, 257/E23.011, 257690-693
• US Class Current: 257/693
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]

Abstract

A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad.

Claims

1. A device comprising:

a semiconductor substrate comprising a front surface and a back surface opposite the front surface;

an insulation region extending from the front surface into the semiconductor substrate;

an inter-layer dielectric (ILD) over the insulation region;

a landing pad extending from a top surface of the ILD into the insulation region; and

a through-substrate via (TSV) extending from the back surface of the semiconductor substrate to the landing pad.

2. The device of claim 1 further comprising:

a bottom metal layer over the ILD; and

a metal pad in the bottom metal layer and contacting the landing pad.

3. The device of claim 1, wherein the landing pad extends into an upper portion of, and is encircled by, the insulation region, and the TSV extends into a lower portion of the insulation region.

4. The device of claim 3, wherein the landing pad comprises a conductive barrier layer contacting the insulation region.

5. The device of claim 1, wherein the landing pad penetrates through, and is encircled by, the insulation region, with a bottom surface of the landing pad being level with or lower than a bottom surface of the insulation region.

6. The device of claim 5, wherein the landing pad comprises a conductive barrier layer, wherein the device further comprises a dielectric liner between and contacting the conductive barrier layer and the insulation region, and wherein the TSV penetrates through the dielectric liner.

7. The device of claim 1, wherein the landing pad comprises a conductive barrier layer, and wherein the TSV contacts a bottom surface of the conductive barrier layer.

8. The device of claim 1, wherein the landing pad comprises a conductive barrier layer, and wherein the TSV penetrates through the conductive barrier layer.

9. The device of claim 1 further comprising a transistor comprising a gate electrode in the ILD, and a gate contact plug in the ILD and connected to the gate electrode.

10. A device comprising:

a semiconductor substrate comprising a front surface and a back surface opposite the front surface;

a shallow trench isolation (STI) region extending from the front surface into the semiconductor substrate, wherein the STI region comprises a top surface and a bottom surface;

an inter-layer dielectric (ILD) over the STI region;

a landing pad extending from a top surface of the ILD into the STI region, wherein a bottom surface of the landing pad is vertically between the top surface and the bottom surface of the STI region, and wherein the landing pad is encircled by the STI region; and

a through-substrate via (TSV) extending from the back surface of the semiconductor substrate to the landing pad, wherein the TSV penetrates through a lower portion of the STI region to contact the landing pad.

11. The device of claim 10 further comprising:

a bottom metal layer over the ILD; and

a metal pad in the bottom metal layer and contacting the landing pad.

12. The device of claim 10, wherein the landing pad comprises a conductive barrier layer contacting the STI region.

13. The device of claim 12, wherein the TSV contacts a bottom surface of the conductive barrier layer.

14. The device of claim 12, wherein the TSV penetrates through the conductive barrier layer.

15. The device of claim 10, wherein a sidewall of the landing pad extending from a top surface to the bottom surface of the landing pad is substantially straight.

16. A method comprising:

providing a semiconductor substrate comprising a front surface and a back surface opposite the front surface;

forming an insulation region extending from the front surface into the semiconductor substrate;

forming an inter-layer dielectric (ILD) over the insulation region;

etching the ILD and the insulation region to form an opening in the ILD and the insulation region;

filling the opening with a conductive material to form a landing pad;

forming a bottom metal layer over the ILD, wherein the bottom metal layer comprises a metal feature over and electrically coupled to the landing pad; and

forming a TSV extending from the back surface of the semiconductor substrate to electrically coupled to the landing pad.

17. The method of claim 16, wherein the step of forming the TSV comprises:

after the step of forming the landing pad, etching the semiconductor substrate from the back surface of the semiconductor substrate to form an opening, until the landing pad is exposed; and

filling a metallic material into the opening to form the TSV.

18. The method of claim 16, wherein a bottom surface of the opening in the ILD and the insulation region is higher than a bottom surface of the insulation region, and wherein the step of forming the TSV comprises etching a lower portion of the insulation region.

19. The method of claim 16, wherein a bottom surface of the opening in the ILD and the insulation region is level with or lower than a bottom surface of the insulation region.

20. The method of claim 19 further comprising forming a dielectric liner between the landing pad and the semiconductor substrate.