Simplified pitch doubling process flow

• US 8,338,959 B2
• Filed: 09/12/2011
• Issued: 12/25/2012
• Est. Priority Date: 04/07/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Niroomand, Ardavan, Zhou, Baosuo, Alapati, Ramakanth
• Primary Examiner(s): Lee, Jae
• Application Number:
  US13/229,898
• Publication Number:
  US 20110316114A1
• Time in Patent Office: 470 Days
• Field of Search: 438/726, 438/706, 257/E21.038, 257/E21.039, 257/773, 257/774
• US Class Current: 257/774
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

Claims

1. A partially formed integrated circuit, comprising:

a substrate;

a hard mask layer disposed over the substrate;

a plurality of mandrels comprising photoresist and extending over the hard mask layer;

a plurality of spacer loops disposed at sidewalls of the mandrels and directly over the hard mask layer, and at least partially disposed in an array region of the partially formed integrated circuit; and

a mask at least partially defined in a peripheral region of the partially formed integrated circuit, wherein the mask is also directly disposed over the hard mask layer, wherein each of the plurality of spacer loops includes a looped end, and wherein the mask overlaps at least one of the looped ends while leaving central portions of the spacer loops exposed.

2. The partially formed integrated circuit of claim 1, wherein material forming the spacer loops extends between the hard mask layer and the mask.

3. The partially formed integrated circuit of claim 1, wherein at least a portion of the plurality of spacer loops and the mask are in a common plane displaced from the substrate.

4. The partially formed integrated circuit of claim 1, further comprising an amorphous carbon layer positioned between the substrate and the hard mask layer.

5. The partially formed integrated circuit of claim 1, wherein the substrate comprises a plurality of layers of different materials.

6. The partially formed integrated circuit of claim 5, wherein the plurality of layers corresponds to layers in a control gate stack.

7. The partially formed integrated circuit of claim 1, wherein the partially formed integrated circuit is a partially formed device selected from the group consisting of a memory device and a computer processor.

8. The partially formed integrated circuit of claim 1, wherein the plurality of spacer loops and the mask comprise an oxide material.

9. The partially formed integrated circuit of claim 1, wherein the mask comprises a spin-on antireflective coating.

10. The partially formed integrated circuit of claim 1, wherein the mask further defines a pattern of features in the peripheral region of the partially formed integrated circuit, the features being selected from the group consisting of a landing pad, a transistor and an interconnect.

11. The method of claim 1, wherein the mandrels extend in parallel, regularly spaced-apart lines.

12. The partially formed integrated circuit of claim 1, wherein the plurality of photoresist mandrels form a pattern having a pitch between about 70 nm and about 120 nm.

13. The partially formed integrated circuit of claim 12, wherein the plurality of photoresist mandrels form a pattern having a pitch between about 80 nm and about 100 nm.

14. A partially formed integrated circuit, comprising:

a substrate;

a plurality of photoresist mandrels over the substrate;

a plurality of spacer loops formed of spacer material and disposed at sidewalls of each of the mandrels, the spacer loops extending at least partly in an array region of the partially formed integrated circuit;

a mask extending at least partly in a peripheral region of the partially formed integrated circuit, wherein the mask overlaps one or more ends of the spacer loops while leaving central portions of the spacer loops exposed; and

a layer of spacer material extending between the substrate and portions of the mask in the peripheral region.

15. The partially formed integrated circuit of claim 14, wherein the mask comprises photoresist.

16. The partially formed integrated circuit of claim 14, wherein the mask defines an opening extending over the array region.

17. The partially formed integrated circuit of claim 14, further comprising a plurality of hardmask layers disposed between the spacer loops and the substrate.

18. The partially formed integrated circuit of claim 17, wherein the plurality of hardmask layers includes an amorphous carbon layer.

19. The method of claim 14, wherein the mandrels are defined by elongate lines of photoresist.