High-speed ceramic modules with hybrid referencing scheme for improved performance and reduced cost

• US 8,339,803 B2
• Filed: 12/04/2009
• Issued: 12/25/2012
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Becker, Wiren Dale, Choi, Jinwoo, Zhou, Tingdong
• Primary Examiner(s): Dinh, Tuan T
• Assistant Examiner(s): SAWYER, STEVEN T
• Application Number:
  US12/630,993
• Publication Number:
  US 20110132650A1
• Time in Patent Office: 1,117 Days
• Field of Search: 361/780
• US Class Current: 361/780
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/19051 Impedance matching structure [e.g. balun]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0253 Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings H05K1/0251 takes precedence
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/09681 Mesh conductors, e.g. as a ground plane
• CPC Class Codes: H05K 2201/09727 Varying width along a single conductor; Conductors or pads having different widths
• CPC Class Codes: H05K 2201/10674 Flip chip
• CPC Class Codes: H05K 3/4629 laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises different mesh configurations from among: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas, and the Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.

Claims

1. A multi-layered ceramic package comprising:

a signal layer having one or more high power usage (HPU) areas and one or more second areas that are not HPU areas, wherein the HPU areas provide a supply of power for operation of one or more devices located within the HPU areas; and

a reference mesh layer disposed immediately adjacent to and on a same side as a first side of the signal layer and which provides a first reference mesh plane and is configured according to a hybrid mesh scheme;

a ground (Gnd) mesh layer, disposed immediately adjacent to and on a same side as a second side of the signal layer, wherein the second side is on an opposite side of the signal layer from the first side, and wherein the Gnd mesh layer comprises a second reference mesh plane that is also configured according to the hybrid mesh scheme;

wherein the hybrid mesh scheme comprises;

a full dense mesh within only a first one or more areas of the reference mesh layer that are directly adjacent to the one or more HPU areas in the signal layer, a half dense mesh in one or more second areas within the reference mesh layer that are adjacent to one or more perimeter edges of and proximate to the one or more HPU areas in the signal layer, and a low density mesh in all other areas within the reference mesh layer that are not adjacent or proximate to the one or more HPU areas of the signal layer;

wherein;

the reference mesh layer is a voltage power (Vdd) mesh layer and the ceramic package further comprises a plurality of Gnd vias that extend through the first and second reference mesh planes and are coupled to the Gnd mesh layer.

2. The multi-layered ceramic package of claim 1, wherein:

the reference mesh layer is a Vdd mesh layer and all Vdd traces in the other areas of the Vdd mesh layer run parallel to adjacent signal lines of the signal layer; and

the parallel, adjacent Vdd traces reduce discontinuity on the return path and results in less far end (FE) crosstalk.

3. The multi-layered ceramic package of claim 1, wherein the ceramic package further comprises:

a plurality of Vdd vias extending through the first and second reference mesh planes and coupled to the Vdd mesh layer;

wherein a Vdd mesh trace of a Vdd reference mesh that is adjacent to a parallel signal line in the signal layer and is not in a HPU area is coupled to one or more Vdd vias that is close to the Vdd mesh trace; and

wherein each parallel Vdd trace and Gnd trace adjacent to a single line that is not in the one or more HPU areas is coupled to a corresponding Vdd via or Gnd via that surrounds the signal line to close a return path.

4. The multi-layered ceramic package of claim 1, wherein further the hybrid mesh scheme comprises:

a first set of Vdd and Gnd traces within respective reference mesh layer and Gnd mesh layer that are adjacent to the one or more HPU areas and are configured with a first width; and

one or more of a second set of traces corresponding to the Vdd and Gnd traces located in the other areas and running parallel to adjacent signal lines are configured with a second width that is larger than the first width;

wherein the second width is N times larger than the first width, where N is a real number.

5. The multi-layered ceramic package of claim 1, further comprising one or more matched impedances coupled to at least a driver side of one or more signal traces to reduce a near end crosstalk within the ceramic package.

6. The multi-layered ceramic package of claim 1, wherein said hybrid mesh scheme further comprises:

a first mesh pitch for Vdd and Gnd traces adjacent to the other areas of the signal layer that are not HPU areas, wherein the first mesh pitch is larger than a second mesh pitch of Vdd and Gnd traces adjacent to the HPU areas and the perimeter edges of the HPU areas;

wherein configuration of a larger mesh pitch for Vdd and Gnd traces adjacent to the other areas substantially reduces far-end noise within the ceramic package.

7. The multi-layered ceramic package of claim 1, wherein the multi-layered ceramic package is a glass-ceramic package.

8. An integrated circuit (IC) manufactured using the multi-layered ceramic package of claim 1, the IC comprising one or more devices or chips attached to the one or more HPU areas.

9. The multi-layered ceramic package of claim 1, wherein:

the first side of the signal layer is directly above the signal layer; and

the second side of the signal layer is directly below the signal layer.

10. The multi-layered ceramic package of claim 1, wherein:

the first side of the signal layer is directly below the signal layer; and

the second side of the signal layer is directly above the signal layer.

11. The multi-layered ceramic package of claim 4, wherein a width of the signal lines and a dielectric material thickness are optimized to obtain a desired impedance of the signal lines.

12. The multi-layered ceramic package of claim 6, wherein said first mesh pitch is twice as large as said second mesh pitch.

13. The multi-layered ceramic package of claim 6, wherein the low density mesh comprises only reference traces that are parallel to adjacent signal lines running on the signal layer.