Semiconductor device

• US 8,339,828 B2
• Filed: 11/17/2010
• Issued: 12/25/2012
• Est. Priority Date: 11/20/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US12/947,846
• Publication Number:
  US 20110122670A1
• Time in Patent Office: 769 Days
• Field of Search: 365/72, 365/63, 365/145, 365/189.09, 365/189.11, 365/230.06, 365/227
• US Class Current: 365/72
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/22 including, apart from doping materials or other impurities, only AIIBVI compounds
• CPC Class Codes: H01L 29/24 : including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/26 : including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 , e.g. alloys
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/70 : the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.

Claims

1. A semiconductor device comprising:

a source line;

a bit line;

first signal lines;

second signal lines;

word lines;

memory cells connected in parallel between the source line and the bit line;

a potential generating circuit generating and supplying writing potentials and reference potentials;

a boosting circuit supplying a potential to the potential generating circuit;

a first driver circuit configured to drive the second signal lines and the word lines to select, according to an address signal, a memory cell connected to the bit line;

a second driver circuit configured to select a first signal line and output any of the writing potentials to the selected first signal line; and

a reading circuit to which a potential of the bit line and the reference potentials are input and configured to determine a data stored in a selected memory cell according to the potential of the bit line and the reference potentials,

wherein one of the memory cells includes;

a first transistor formed on a substrate and having a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and

a third transistor having a third gate electrode, a third source electrode, and a third drain electrode,

wherein the second transistor includes an oxide semiconductor layer,

wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the source line and the first source electrode are electrically connected to each other,

wherein the first drain electrode and the third source electrode are electrically connected to each other,

wherein the bit line and the third drain electrode are electrically connected to each other,

wherein one of the first signal lines and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein one of the second signal lines and the second gate electrode are electrically connected to each other, and

wherein one of the word lines and the third gate electrode are electrically connected to each other.

2. The semiconductor device according to claim 1, further comprising a capacitor having one electrode electrically connected to the first gate electrode and to the one of the second source electrode and the second drain electrode and another electrode connected to a predetermined potential.

3. The semiconductor device according to claim 1,

wherein the reading circuit is configured to determine data stored in the selected memory cell by comparing the potential of the bit line to the reference potentials.

4. The semiconductor device according to claim 1 further comprising a reference memory cell,

wherein the reading circuit is configured to determine data stored in the selected memory cell by comparing a voltage of the bit line connected to the selected memory cell to a voltage output by the reference memory cell.

7. The semiconductor device according to claim 1, wherein the substrate contains a semiconductor material and the first transistor includes a channel formation region provided in the substrate, impurity regions formed with the channel formation region sandwiched therebetween, a first gate insulating layer over the channel formation region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode electrically connected to the impurity regions.

9. The semiconductor device according to claim 1, wherein the second transistor includes the second gate electrode over the substrate, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.

11. The semiconductor device according to claim 1, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

13. The semiconductor device according to claim 1, wherein the substrate contains silicon.

15. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is formed using an In—

Ga—

Zn—

O-based oxide semiconductor material.

17. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

19. The semiconductor device according to claim 1, wherein a hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

21. The semiconductor device according to claim 1, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

5. A semiconductor device comprising:

a source line;

a bit line;

first signal lines;

second signal lines;

word lines;

memory cells connected in parallel between the source line and the bit line;

a potential generating circuit generating and supplying writing potentials and reference potentials;

a boosting circuit supplying a potential to the potential generating circuit;

a first driver circuit to which an address signal and the reference potentials are input and which is configured to drive the second signal lines and the word lines so as to select, according to the address signal, a memory cell connected to the bit line and to select and output any of the reference potentials to a selected word line;

a second driver circuit configured to select a first signal line and output any of the writing potentials to the selected first signal line; and

a reading circuit to which the bit line is connected, and configured to determine a data stored in a selected memory cell according to the potential of the bit line,

wherein one of the memory cells includes;

a first transistor formed on a substrate and having a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and

a capacitor,

wherein the second transistor includes an oxide semiconductor layer,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and an electrode of the capacitor are electrically connected to one another,

wherein the source line and the first source electrode are electrically connected to each other,

wherein the bit line and the first drain electrode are electrically connected to each other,

wherein one of the first signal lines and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein one of the second signal lines and the second gate electrode are electrically connected to each other, and

wherein one of the word lines and another electrode of the capacitor are electrically connected to each other.

6. The semiconductor device according to claim 5,

wherein the reading circuit is configured to determine data stored in the selected memory cell by comparing the potential of the bit line to one or more reference potentials inputted in the reading circuit.

8. The semiconductor device according to claim 5, wherein the substrate contains a semiconductor material and the first transistor includes a channel formation region provided in the substrate, impurity regions formed with the channel formation region sandwiched therebetween, a first gate insulating layer over the channel formation region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode electrically connected to the impurity regions.

10. The semiconductor device according to claim 5, wherein the second transistor includes the second gate electrode over the substrate, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.

12. The semiconductor device according to claim 5, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

14. The semiconductor device according to claim 5, wherein the substrate contains silicon.

16. The semiconductor device according to claim 5, wherein the oxide semiconductor layer is formed using an In—

Ga—

Zn—

O-based oxide semiconductor material.

18. The semiconductor device according to claim 5, wherein the oxide semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

20. The semiconductor device according to claim 5, wherein a hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

22. The semiconductor device according to claim 5, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

23. A semiconductor device comprising:

a source line;

a bit line;

first signal lines;

second signal lines;

word lines;

memory cells connected in parallel between the source line and the bit line;

a potential generating circuit generating and supplying writing potentials and reference potentials;

a boosting circuit supplying a potential to the potential generating circuit;

a first driver circuit configured to drive the second signal lines and the word lines to select, according to an address signal, a memory cell connected to the bit line;

a second driver circuit configured to select a first signal line and output any of the writing potentials to the selected first signal line; and

a reading circuit to which a potential of the bit line and the reference potentials are input and configured to determine a data stored in a selected memory cell according to the potential of the bit line and the reference potentials,

wherein one of the memory cells includes;

a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and

a third transistor having a third gate electrode, a third source electrode, and a third drain electrode,

wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the source line and the first source electrode are electrically connected to each other,

wherein the first drain electrode and the third source electrode are electrically connected to each other,

wherein the bit line and the third drain electrode are electrically connected to each other,

wherein one of the first signal lines and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein one of the second signal lines and the second gate electrode are electrically connected to each other, and

wherein one of the word lines and the third gate electrode are electrically connected to each other.

24. A semiconductor device comprising:

a source line;

a bit line;

first signal lines;

second signal lines;

word lines;

memory cells connected in parallel between the source line and the bit line;

a potential generating circuit generating and supplying writing potentials and reference potentials;

a boosting circuit supplying a potential to the potential generating circuit;

a first driver circuit to which an address signal and the reference potentials are input and which is configured to drive the second signal lines and the word lines so as to select, according to the address signal, a memory cell connected to the bit line and to select and output any of the reference potentials to a selected word line;

a second driver circuit configured to select a first signal line and output any of the writing potentials to the selected first signal line; and

a reading circuit to which the bit line is connected, and configured to determine a data stored in a selected memory cell according to the potential of the bit line,

wherein one of the memory cells includes;

a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and

a capacitor,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and an electrode of the capacitor are electrically connected to one another,

wherein the source line and the first source electrode are electrically connected to each other,

wherein the bit line and the first drain electrode are electrically connected to each other,

wherein one of the first signal lines and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein one of the second signal lines and the second gate electrode are electrically connected to each other, and

wherein one of the word lines and another electrode of the capacitor are electrically connected to each other.