Write-once nonvolatile memory with redundancy capability

• US 8,339,832 B2
• Filed: 04/08/2010
• Issued: 12/25/2012
• Est. Priority Date: 12/28/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US12/756,342
• Publication Number:
  US 20100195367A1
• Time in Patent Office: 992 Days
• Field of Search: 365/104, 365/103, 365/100, 365/148, 365/163, 365/96, 365/94, 365/185.09, 365/185.22, 365/200, 365/201, 365/233.16, 365/233.17, 365/233.19, 365/151, 365/153, 365/233.1, 365/192, 365/197, 365/198, 365/191
• US Class Current: 365/104
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/787 using a fuse hierarchy
• CPC Class Codes: G11C 29/816 for an application-specific layout
• CPC Class Codes: G11C 29/848 by adjacent switching
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate

Abstract

A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus, it is difficult to provide a memory with few defects. It is an object of the present invention to provide a write-once memory where the probability of a defect is reduced considerably. A nonvolatile memory that can be written only once includes a redundant memory cell, a first circuit which allocates an address to the redundant memory cell, a second circuit which outputs a determination signal that expresses whether writing is performed normally or not, and a third circuit, to which the determination signal is inputted, which controls the first circuit and the second circuit.

Claims

1. A memory device comprising:

a memory cell array comprising;

a plurality of first memory cells; and

at least one second memory cell;

a first reading writing circuit for writing data to the plurality of first memory cells and the second memory cell;

a second writing circuit;

a verify circuit for confirming whether the data is normally stored in the plurality of first memory cells; and

a timing control circuit coupled with and arranged to control the first reading writing circuit, the second writing circuit, and the verify circuit,

wherein, when the writing of data to one of the plurality of first memory cells fails, the second writing circuit is arranged to assign an address of the one of the plurality of first memory cells to the second memory cell, and

wherein the plurality of first memory cells and the second memory cell are arranged to irreversibly change an electrical resistance thereof when the data is stored therein.

2. The memory device according to claim 1, further comprising an antenna which is capable of receiving an electric wave.

3. The memory device according to claim 1,

wherein each of the plurality of first memory cells and the second memory cell is a write-once memory to which the data can be written only once.

4. The memory device according to claim 1,

wherein the memory device is formed over a flexible substrate.

5. The memory device according to claim 1,

wherein the first reading writing circuit is arranged to write data to the second memory cell to which the address is assigned.

6. The memory device according to claim 1,

wherein each of the plurality of first memory cells and the second memory cell has a thin film transistor comprising an oxide semiconductor.

7. The memory device according to claim 6,

wherein the oxide semiconductor comprises zinc oxide.

8. The memory device according to claim 6,

wherein the oxide semiconductor comprises zinc oxide and is doped with indium.

9. The memory device according to claim 6,

wherein the oxide semiconductor comprises zinc oxide and is doped with gallium.