Semiconductor memory device

• US 8,339,883 B2
• Filed: 11/17/2010
• Issued: 12/25/2012
• Est. Priority Date: 11/18/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yu, Je-min, Kim, Byung-chul, Kim, Jun-hyung, Hwang, Sang-joon
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US12/948,302
• Publication Number:
  US 20110116334A1
• Time in Patent Office: 769 Days
• Field of Search: 365/203, 365/204, 365/205, 365/207, 365/222, 365/185.11, 365/185.13, 365/185.23
• US Class Current: 365/203
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A semiconductor memory device includes a bitline sensing amp detecting and amplifying data of a pair of bitlines from a memory cell, a column selecting unit transmitting the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal, a dataline precharging unit precharging the pair of local datalines to a precharging voltage level in response to a precharging signal, and a dataline sensing amp detecting and amplifying data transmitted to the pair of local datalines. The dataline sensing amp includes a charge sync unit discharging the pair of local datalines at the precharging voltage level in response to a first dataline sensing enabling signal and data of the pair of local datalines, and a data sensing unit transmitting data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.

Claims

1. A semiconductor memory device comprising:

a bitline sensing amp configured to detect and amplify data of a pair of bitlines, the data of the pair of bitlines being memory cell data transmitted to the pair of bitlines;

a column selecting unit configured to transmit the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal;

a dataline precharging unit configured to precharge the pair of local datalines to a precharging voltage level in response to a precharging signal; and

a dataline sensing amp configured to detect and amplify data of the pair of local datalines,

wherein the dataline sensing amp includes;

a charge sync unit configured to discharge charges of the pair of local datalines at the precharging voltage level in response to a first dataline sensing enabling signal and the data of the pair of local datalines; and

a data sensing unit configured to transmit data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.

2. The semiconductor memory device as claimed in claim 1, wherein the charge sync unit detects and amplifies the data of the pair of local datalines.

3. The semiconductor memory device as claimed in claim 1, wherein the first dataline sensing enabling signal is simultaneously activated with the column selecting signal.

4. The semiconductor memory device as claimed in claim 1, wherein the first dataline sensing enabling signal is activated before the second dataline sensing enabling signal is activated.

5. The semiconductor memory device as claimed in claim 1, wherein the first dataline sensing enabling signal is simultaneously activated with the second dataline sensing enabling signal.

6. The semiconductor memory device as claimed in claim 1, wherein the first dataline sensing enabling signal is activated after the second dataline sensing enabling signal is activated.

7. The semiconductor memory device as claimed in claim 1, wherein the charge sync unit includes:

a first NMOS transistor, a gate of the first NMOS transistor being connected to a local dataline and a drain of the first NMOS transistor being connected to a complementary local dataline;

a second NMOS transistor, a gate of the second NMOS transistor being connected to the complementary local dataline and a drain of the second NMOS transistor being connected to the local dataline; and

a third NMOS transistor, a drain of the third NMOS transistor being connected to sources of the first and second NMOS transistors, the first dataline sensing enabling signal being input to a gate of the third NMOS transistor, and a source of the third NMOS transistor being grounded.

8. The semiconductor memory device as claimed in claim 1, wherein the data sensing unit includes:

a first NMOS transistor, the second dataline sensing enabling signal being input to a gate of the first NMOS transistor, and the complementary global dataline being connected to a drain of the first NMOS transistor;

a second NMOS transistor, the second dataline sensing enabling signal being input to a gate of the second NMOS transistor, and the global dataline being connected to a drain of the second NMOS transistor;

a third NMOS transistor, the local dataline being connected to a gate of the third NMOS transistor, and a source of the first NMOS transistor being connected to a drain of the third NMOS transistor;

a fourth NMOS transistor, the complementary local dataline being connected to a gate of the fourth NMOS transistor, and a source of the second NMOS transistor being connected to a drain of the fourth NMOS transistor; and

a fifth NMOS transistor, the sources of the third and fourth NMOS transistors being connected to a drain of the fifth NMOS transistor, the second dataline enabling sensing enabling signal being input to a gate of the fifth NMOS transistor, and a ground voltage VSS being input to a source of the fifth NMOS transistor.

9. A semiconductor memory device comprising:

a bitline sensing amp configured to detect and amplify data of a pair of bitlines, the data of the pair of bitlines being memory cell data transmitted to the pair of bitlines;

a column selecting unit configured to transmit the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal;

a dataline precharging unit configured to precharge the pair of local datalines to a precharging voltage level in response to a precharging signal; and

a dataline sensing amp configured to detect and amplify data of the pair of local datalines,

wherein the dataline sensing amp comprises;

a sensing control unit configured to generate an inversed dataline sensing enabling signal in response to a first dataline sensing enabling signal;

a charge sync unit configured to discharge charges of the pair of local datalines at the precharging voltage level in response to the first dataline sensing enabling signal, the inversed dataline sensing enabling signal, and the data of the pair of local datalines; and

a data sensing unit configured to transmit the data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.

10. The semiconductor memory device as claimed in claim 9, wherein the charge sync unit detects and amplifies the data of the pair of local datalines.

11. The semiconductor memory device as claimed in claim 9, wherein the first dataline sensing enabling signal is simultaneously activated with the column selecting signal.

12. The semiconductor memory device as claimed in claim 9, wherein the charge sync unit includes:

a first PMOS transistor, the inversed dataline sensing enabling signal being input to a gate of the first PMOS transistor, and a power voltage being input to a source of the first PMOS transistor;

a first NMOS transistor, the dataline sensing enabling signal being input to a gate of the second NMOS transistor, and a ground voltage being input to a source of the second NMOS transistor;

a second PMOS transistor interconnected between a drain of the first PMOS transistor and a local dataline, and a complementary local dataline is connected to a gate of the second PMOS transistor;

a third PMOS transistor interconnected between a drain of the first PMOS transistor and the complementary local dataline, the local dataline being connected to a source of the third PMOS transistor;

a second NMOS transistor interconnected between a drain of the first NMOS transistor and the local dataline, the complementary local dataline being connected to a gate of the second NMOS transistor; and

a third NMOS transistor interconnected between the drain of the first NMOS transistor and the complementary local dataline, the local dataline being connected to a gate of the third NMOS transistor.

13. The semiconductor memory device as claimed in claim 9, wherein the data sensing unit includes:

a first NMOS transistor, the dataline sensing enabling signal being input to a gate of the first NMOS transistor, and a complementary global dataline being connected to a drain of the first NMOS transistor;

a second NMOS transistor, the dataline sensing enabling signal being input to a gate of the second NMOS transistor, and the global dataline being connected to a drain of the second NMOS transistor;

a third NMOS transistor, a local dataline being connected to a gate of the third NMOS transistor, and a source of the first NMOS transistor being connected to a drain of the third NMOS transistor;

a fourth NMOS transistor, the complementary local dataline being connected to a gate of the fourth NMOS transistor, and a source of the second NMOS transistor being connected to a drain of the fourth NMOS transistor; and

a fifth NMOS transistor, the sources of the third and fourth NMOS transistors being connected to a drain of the fifth NMOS transistor, the dataline enabling sensing enabling signal being input to a gate of the fifth NMOS transistor, and the ground voltage VSS being input to a source of the fifth NMOS transistor.

14. A method of operating a semiconductor memory device, the method comprising:

precharging a pair of local datalines to a precharging voltage level in response to a precharging signal;

detecting and amplifying memory cell data transmitted to a pair of bitlines;

transmitting data of the pair of bitlines to the pair of local datalines in response to a column selecting signal;

detecting and amplifying data of the pair of local datalines;

discharging charges of the pair of local datalines at a precharging voltage level in response to a first dataline sensing enabling signal and the data of the pair of local datalines; and

transmitting the data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.

15. The method as claimed in claim 14, wherein the first dataline sensing enabling signal is simultaneously activated with the column selecting signal.

16. The method as claimed in claim 14, wherein the first dataline sensing enabling signal is activated before the second dataline sensing enabling signal is activated.

17. The method as claimed in claim 14, wherein the first dataline sensing enabling signal is simultaneously activated with the second dataline sensing enabling signal.

18. The method as claimed in claim 14, wherein the first dataline sensing enabling signal is activated after the second dataline sensing enabling signal is activated.

19. A method of operating a semiconductor memory device, the method comprising:

precharging a pair of local datalines to a precharging voltage level in response to a precharging signal;

detecting and amplifying memory cell data transmitted to a pair of bitlines;

transmitting data of the pair of bitlines to the pair of local datalines in response to a column selecting signal;

detecting and amplifying data of the pair of local datalines;

discharging charges of the pair of local datalines at a precharging voltage level in response to a first dataline sensing enabling signal and an inversed dataline sensing enabling signal; and

transmitting the data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.

20. The method as claimed in claim 19, wherein the first dataline sensing enabling signal is simultaneously activated with the column selecting signal.