Methods and apparatus related to a low cost data center architecture
First Claim
1. An apparatus, comprising:
- a first edge device having a packet processing module, the first edge device configured to receive a packet, the packet processing module of the first edge device configured to produce a plurality of cells based on the packet,the first edge device including a buffer configured to define a queue having a length associated with a grant-request scheme;
a second edge device having a packet processing module configured to reassemble the packet based on the plurality of cells; and
a multi-stage switch fabric coupled to the first edge device and the second edge device, the multi-stage switch fabric defining a single logical entity, the multi-stage switch fabric having a plurality of switch modules, each switch module from the plurality of switch modules having a shared memory device, the multi-stage switch fabric configured to switch the plurality of cells so that the plurality of cells are sent to the second edge device,each switch module from the plurality of switch modules excluding a buffer configured to define a queue associated with the grant-request scheme.
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Abstract
In one embodiment, an apparatus can include a first edge device that can have a packet processing module. The first edge device can be configured to receive a packet. The packet processing module of the first edge device can be configured to produce cells based on the packet. A second edge device can have a packet processing module configured to reassemble the packet based on the cells. A multi-stage switch fabric can be coupled to the first edge device and the second edge device. The multi-stage switch fabric can define a single logical entity. The multi-stage switch fabric can have switch modules. Each switch module from the switch modules can have a shared memory device. The multi-stage switch fabric can be configured to switch the cells so that the cells are sent to the second edge device.
136 Citations
18 Claims
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1. An apparatus, comprising:
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a first edge device having a packet processing module, the first edge device configured to receive a packet, the packet processing module of the first edge device configured to produce a plurality of cells based on the packet, the first edge device including a buffer configured to define a queue having a length associated with a grant-request scheme; a second edge device having a packet processing module configured to reassemble the packet based on the plurality of cells; and a multi-stage switch fabric coupled to the first edge device and the second edge device, the multi-stage switch fabric defining a single logical entity, the multi-stage switch fabric having a plurality of switch modules, each switch module from the plurality of switch modules having a shared memory device, the multi-stage switch fabric configured to switch the plurality of cells so that the plurality of cells are sent to the second edge device, each switch module from the plurality of switch modules excluding a buffer configured to define a queue associated with the grant-request scheme. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus, comprising:
a multi-stage switch fabric defining a single logical entity, the multi-stage switch fabric configured to be coupled to a first edge device and a second edge device, the multi-stage switch fabric including a plurality of switch modules, each switch module from the plurality of switch modules including a shared memory device configured to define a queue having a length sufficient for the multi-stage switch fabric to implement cell-switching synchronization and insufficient for the multi-stage switch fabric to implement a congestion resolution scheme at that switch module. - View Dependent Claims (9, 10, 11)
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12. A method, comprising:
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receiving a plurality of cells at a plurality of input ports of a multi-stage switch fabric, each cell from the plurality of cells being associated with a packet from a plurality of packets received by a plurality of ingress edge devices; and switching each cell from the plurality of cells through a multi-stage switch fabric without performing Ethernet-based processing within the multi-stage switch fabric, the multi-stage switch fabric defining a single Ethernet hop between the plurality of ingress edge devices and a plurality of egress edge devices, the multi-stage switch fabric having a plurality of switch modules, each switch module from the plurality of switch modules having a shared memory device, the switching includes buffering the plurality of cells within the shared memory devices of the plurality of switch modules to correct for cell-switching synchronization without resolving congestion within the multi-stage switch fabric according to a grant-request scheme. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification