Memory circuit simulation with power saving capabilities

• US 8,340,953 B2
• Filed: 10/26/2006
• Issued: 12/25/2012
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Schakel, Keith R., Smith, Michael John Sebastian, Wang, David T., Weber, Frederick Daniel
• Primary Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US11/553,372
• Publication Number:
  US 20080027697A1
• Time in Patent Office: 2,252 Days
• Field of Search: 703/13, 703/14, 711/103, 711/110
• US Class Current: 703/14
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A system and method are provided including a component in communication with a plurality of memory circuits and a system. The component is operable to interface the memory circuits an the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The component is further operable to perform a power saving operation.

Claims

1. A memory apparatus for use with a host system, the memory apparatus comprising:

a plurality of physical memory circuits;

a component coupled to the plurality of physical memory circuits and couplable to the host system to provide an interface between the host system and the plurality of physical memory circuits, wherein the component is operable to;

provide to the host system an interface to a simulated memory circuit that differs in at least one aspect from a corresponding aspect of at least one of the plurality of physical memory circuits; and

for each physical memory circuit of the plurality of physical memory circuits coupled to the component, (1) determine whether the physical memory circuit is being accessed, and (2) perform a power-saving operation on the physical memory circuit, subsequent to determining that the physical memory circuit is not being accessed, to reduce a power dissipation of the physical memory circuit,

wherein the plurality of physical memory circuits comprises a first number (P) of physical memory circuits, and the memory apparatus is operable such that a second number (N) of physical memory circuits is continuously subjected to the power-saving operation, wherein N<

P.

2. The memory apparatus of claim 1, wherein the power-saving operation comprises a power-down operation.

3. The memory apparatus of claim 2, wherein the power-down operation comprises a precharge power-down operation.

4. The memory apparatus of claim 1, wherein determining whether the physical memory circuit is being accessed includes determining whether a portion of the physical memory circuit is being accessed.

5. The memory apparatus of claim 1, wherein the component is operable to perform the power-saving operation by controlling an enable pin.

6. The memory apparatus of claim 5, wherein the enable pin comprises a clock-enable pin.

7. The memory apparatus of claim 1, wherein the at least one aspect comprises a timing.

8. The memory apparatus of claim 1, wherein the at least one aspect comprises a signal.

9. The memory apparatus of claim 1, wherein determining whether the physical memory circuit is being accessed comprises determining whether a page of the physical memory circuit is being accessed.

10. The memory apparatus of claim 1, wherein determining that the physical memory circuit is not being accessed comprises determining that the physical memory circuit has no open pages.

11. A memory apparatus for use with a host system, the memory apparatus comprising:

a plurality of physical memory circuits; and

a component coupled to the plurality of physical memory circuits and couplable to the host system to provide an interface between the host system and the plurality of physical memory circuits,

wherein the component is operable to provide to the host system an interface to a simulated memory circuit that differs in at least one aspect of at least one of the plurality of physical memory circuits,

wherein the component is further operable to perform a power-saving operation on at least a portion of the plurality of physical memory circuits,

wherein the plurality of physical memory circuits comprises a first number (P) of the plurality of physical memory circuits, and the memory apparatus is operable such that a second number (N) of the plurality of physical memory circuits is continuously subjected to the power-saving operation, and

wherein N<

P.

12. The memory apparatus of claim 11, wherein N =P-1.

13. The memory apparatus of claim 11, wherein the power-saving operation comprises a power-down operation.

14. The memory apparatus of claim 13, wherein the power-down operation comprises a precharge power-down operation.

15. The memory apparatus of claim 11, wherein the component is further operable to determine which physical memory circuits to perform the power-saving operation on.

16. The memory apparatus of claim 15, wherein determining which physical memory circuits to perform the power-saving operation on comprises determining which physical memory circuits contain no open pages.

17. The memory apparatus of claim 11, wherein the component is operable to perform the power-saving operation by de-asserting a clock enable input of the physical memory circuit.

18. A memory apparatus for use with an electronic host system, the memory apparatus comprising:

a plurality of physical monolithic memory circuits; and

a component separate from the host system and from the physical memory circuits, the component being operable to communicate electrical signals between the plurality of physical memory circuits and the host system, wherein the component is further operable to;

interface the plurality of physical memory circuits and the host system for simulating at least one memory circuit having a first aspect that is different than a second corresponding aspect of at least one physical memory circuit of the plurality of physical memory circuits; and

for each physical memory circuit of the plurality of physical memory circuits, (1) determine whether the physical memory circuit is being accessed, and (2) perform a power-saving operation upon the physical memory circuit, subsequent to determining that the physical memory circuit is not being accessed, to reduce a power dissipation of the physical memory circuit that is not being accessed.

19. The memory apparatus of claim 18, wherein the first aspect comprises one of a signal, a latency, or a timing.

20. The memory apparatus of claim 18, wherein the power- saving operation comprises a power-down operation.

21. The memory apparatus of claim 20, wherein the power-down operation comprises a precharge power-down operation.

22. The memory apparatus of claim 18, wherein determining whether the physical memory circuit is being accessed comprises determining whether the physical memory circuit contains no open pages.

23. A memory apparatus for use with a host system, the memory apparatus comprising:

a plurality of physical memory circuits; and

a memory controller operable to communicate with the plurality of physical memory circuits and couplable to the host system, wherein the memory controller is operable to;

simulate a memory circuit having at least one aspect that is different from at least one corresponding aspect of at least one physical memory circuit of the plurality of physical memory circuits; and

for each physical memory circuit of the plurality of physical memory circuits, (1) determine whether the physical memory circuit is being accessed, and (2) perform a power-saving operation upon the physical memory circuit, subsequent to determining that the physical memory circuit is not being accessed, to reduce a power dissipation of the physical memory circuit that is not being accessed,

wherein the plurality of physical memory circuits comprises a first number (P) of physical memory circuits, and the memory apparatus is operable such that a second number (N) of physical memory circuits is continuously subjected to the power-saving operation, wherein N<

P.

24. The memory apparatus of claim 23, wherein the at least one aspect of the simulated memory circuit comprises at least one of a signal, a latency, or a timing.

25. The memory apparatus of claim 23, wherein the power- saving operation comprises a power-down operation.

26. The memory apparatus of claim 25, wherein the power-down operation comprises a precharge power-down operation.

27. The memory apparatus of claim 23, wherein determining whether the physical memory circuit is being accessed comprises determining whether the physical memory circuit contains no open pages.

28. A memory apparatus for use with a host system, the memory apparatus comprising:

a plurality of physical monolithic memory circuits;

an advanced memory buffer separate from the host system and from the physical memory circuits, the advanced memory buffer being operable to communicate electrical signals between the plurality of physical memory circuits and the host system, wherein the advanced memory buffer is further operable to;

provide to the host system an interface to a simulated memory circuit, wherein the simulated memory circuit differs from the plurality of physical memory circuits in at least one aspect; and

or each physical memory circuit, (1) determine whether the physical memory circuit is being accessed, and (2) perform a power-saving operation upon the physical memory circuit, subsequent to determining that the physical memory circuit is not being accessed, during a time difference provided by the at least one aspect to reduce a power dissipation of the physical memory circuit.

29. The memory apparatus of claim 28, wherein the power- saving operation comprises a power-down operation.

30. The memory apparatus of claim 29, wherein the power-down operation comprises a precharge power-down operation.

31. The memory apparatus of claim 28, wherein determining whether the physical memory circuit is being accessed comprises determining whether a page of the physical memory circuit is being accessed.

32. The memory apparatus of claim 28, wherein determining that the physical memory circuit is not being accessed comprises determining that the physical memory circuit has no open pages.