System and method for reduced latency data transfers from flash memory to host by utilizing concurrent transfers into RAM buffer memory and FIFO host interface
First Claim
1. A flash memory device comprising:
- a first flash memory for storing non-volatile data for a host;
a host interface for transferring data to the host;
a random-access memory (RAM) for storing data from the flash memory that are to be transferred to the host;
a first-in-first-out memory (FIFO) for receiving data from the flash memory;
a first flash direct-memory access (DMA) engine for receiving and transferring data among the first flash memory, the RAM, and the FIFO, the first flash DMA engine operably connected to the first flash memory via a first flash channel and the flash DMA engine being programmed to transfer data from the first flash memory to the host by transferring data from the first flash memory to the FIFO while simultaneously transferring the data from the first flash memory to RAM; and
a host interface DMA engine for receiving and transferring data among the host interface, RAM, and the FIFO, the host interface DMA engine being programmed to transfer data from the FIFO to the host interface as soon as data is transferred to the FIFO by the first DMA engine and to transfer data from the RAM once the transfer of data from the FIFO has been completed.
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Accused Products
Abstract
A flash memory system having the capability of streaming data directly from flash memory to the interface of a host computer in order to substantially reduce latency of to-host transfers, while also maintaining the capabilities for caching and overlapped flash I/O provided by RAM DMA transfers. When data is read from the flash memory, the data is transferred into the RAM buffer and at the option of the memory controller, directly (via an intermediate FIFO) to the host interface. This results in a desirable reduction in the latency of data transfer because as soon as the first byte of data is read from the flash memory by the DMA engine, the data will be transferred directly to the host interface. Because the data is also being transferred to the buffer RAM, preferred embodiments of the present invention still provide the advantages of using an intermediate transfer buffer.
82 Citations
15 Claims
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1. A flash memory device comprising:
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a first flash memory for storing non-volatile data for a host; a host interface for transferring data to the host; a random-access memory (RAM) for storing data from the flash memory that are to be transferred to the host; a first-in-first-out memory (FIFO) for receiving data from the flash memory; a first flash direct-memory access (DMA) engine for receiving and transferring data among the first flash memory, the RAM, and the FIFO, the first flash DMA engine operably connected to the first flash memory via a first flash channel and the flash DMA engine being programmed to transfer data from the first flash memory to the host by transferring data from the first flash memory to the FIFO while simultaneously transferring the data from the first flash memory to RAM; and a host interface DMA engine for receiving and transferring data among the host interface, RAM, and the FIFO, the host interface DMA engine being programmed to transfer data from the FIFO to the host interface as soon as data is transferred to the FIFO by the first DMA engine and to transfer data from the RAM once the transfer of data from the FIFO has been completed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A nonvolatile memory system comprising:
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a plurality of nonvolatile memory devices comprising a plurality of nonvolatile memory devices each connected to the system via a different corresponding flash channel; a host interface; a buffer memory; and a circuit comprising, for each flash channel, a dedicated flash DMA engine for transferring data from each nonvolatile memory device connected to said flash channel; wherein said host interface is coupled to said circuit and is enabled to receive data from the circuit and transfer the data to a host, wherein said buffer memory is coupled to said circuit and is enabled to receive data from the circuit and transfer the data to a host, wherein said circuit is coupled to each of the plurality of nonvolatile memory devices and is enabled to; (i) stream data from a nonvolatile memory device to the host interface via a first-in-first out memory; (ii) concurrently transfer data from a nonvolatile memory device to the buffer memory; and (iii) transfer data from buffer memory to the host interface when the streaming of data from the nonvolatile memory device to the host interface has been completed; wherein the circuit is coupled to each of the plurality of nonvolatile memory devices via the corresponding flash channels and the circuit is enabled to stream a first portion of sequential data from a nonvolatile memory device on a first flash channel to the host interface via a first-in-first out memory;
concurrently transfer a second portion of data from a nonvolatile memory device on a second flash channel to the buffer memory; and
transfer data from buffer memory to the host interface when the streaming of the first portion of data from the nonvolatile memory device to the host interface has been completed.
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15. A method for accessing flash memory from one or more flash devices by a host computer, comprising:
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concurrently directing a stream of data output from one or more flash devices to both a buffer memory and directly to a host interface comprises; identifying the location of the desired data stored in flash memory; reading the data from flash memory; sending the data directly to a host interface without writing the data into a random-access memory (RAM) buffer and simultaneously writing the data to a RAM buffer; after the data has been sent directly to a host interface, making the data stored in the RAM buffer available for transfer to the host interface; wherein identifying the location of the desired data stored in flash memory comprises identifying the location of a first portion of sequential data stored in flash memory; identifying the location of a second sequential portion of desired data stored in flash memory; reading the second portion of data from flash memory; writing the data to a second RAM buffer; after the first portion of data has been sent directly to a host interface, making the second portion of data stored in the second RAM buffer available for transfer to the host interface; and wherein the first portion of data is stored on flash memory connected to a first flash channel and the second portion of data is stored on flash memory connected to a second flash channel, and in which sending the data directly to a host interface without writing the data into a random-access memory (RAM) buffer comprises; providing a first DMA engine connected to the first flash channel, the first DMA engine configured to transfer the first portion of data to a first-in-first out memory; providing a second flash DMA engine connected to a second flash channel, the second DMA engine configured to transfer the second portion of data to a second RAM buffer; providing a host interface DMA engine, the host interface DMA engine configured to either transfer data from the FIFO to the host interface or to transfer data from the second RAM buffer.
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Specification