Method and apparatus for controlling a translation lookaside buffer

• US 8,341,316 B2
• Filed: 11/17/2010
• Issued: 12/25/2012
• Est. Priority Date: 11/17/2010
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kaplan, David, Bryant, Christopher D., Thompson, Stephen P.
• Primary Examiner(s): Shin, Christopher B
• Application Number:
  US12/948,677
• Publication Number:
  US 20120124325A1
• Time in Patent Office: 769 Days
• Field of Search: 710 5- 7, 710 52- 55, 711203-207, 711/125, 719/314
• US Class Current: 710/55
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Abstract

A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions within a plurality of instructions to be executed, and placing the identified load instructions in a queue prior to execution. An atomic instruction identified in the queue is prevented from executing until the atomic instruction is the oldest instruction in the queue. The apparatus comprises a queue and a translation lookaside buffer. The queue is adapted to: identify an atomic instruction within a plurality of instructions to be executed; prevent execution of the atomic instruction until it is the oldest instruction in the queue; and send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue. The translation lookaside buffer is adapted for maintaining at least one virtual to physical address translation, and is adapted to force a miss in the translation lookaside buffer in response to receiving the atomic load signal.

Claims

1. A method, comprising:

identifying load instructions within a plurality of instructions to be executed;

placing the identified load instructions in a queue prior to execution;

identifying an atomic instruction in the queue; and

preventing execution of the atomic instruction until the atomic instruction is the oldest instruction in the queue.

2. A method, as set forth in claim 1, further comprising:

delivering a virtual address associated with the atomic instruction and an atomic load signal to a translation lookaside buffer containing at least one virtual to physical address translation in response to determining that the atomic instruction is the oldest instruction in the queue; and

forcing a miss in the translation lookaside buffer in response to receiving the atomic load signal.

3. A method, as set forth in claim 2, wherein the translation lookaside buffer includes a first level and a second level translation lookaside buffer and wherein forcing a miss in the translation lookaside buffer further comprises forcing a miss in the first level translation lookaside buffer in response to receiving the atomic load signal.

4. A method, as set forth in claim 3, further comprising inspecting the second level translation lookaside buffer for the virtual to physical address translation corresponding to the atomic instruction in response to the forced miss in the first level translation lookaside buffer.

5. A method, as set forth in claim 4, further comprising sending the virtual to physical address translation corresponding to the atomic instruction from the second level translation lookaside buffer to the first level translation lookaside buffer in response to detecting the virtual to physical address translation corresponding to the atomic instruction in the second level translation lookaside buffer.

6. A method, as set forth in claim 5, further comprising the second level translation lookaside buffer sending a miss signal in response to the detecting that the virtual to physical address translation corresponding to the atomic instruction is absent from the second level translation lookaside buffer, and wherein a tablewalker is adapted to retrieve the virtual to physical address translation corresponding to the atomic instruction from memory in response to receiving the miss signal from the second level translation lookaside buffer.

7. A method, as set forth in claim 6, further comprising inserting the virtual to physical address translation corresponding to the atomic instruction retrieved from memory into the first and second level translation lookaside buffers.

8. A method, as set forth in claim 2, further comprising removing the virtual to physical address translation that corresponds to the atomic instruction from the first level translation lookaside buffer in response to receiving the atomic load signal.

9. A computer readable program storage device encoded with at least one instruction that, when executed by a computer, performs a method, comprising:

identifying load instructions within a plurality of instructions to be executed;

placing the identified load instructions in a queue prior to execution;

identifying an atomic instruction in the queue; and

preventing execution of the atomic instruction until the atomic instruction is the oldest instruction in the queue.

10. A computer readable program storage device, as set forth in claim 9, the method further comprising:

delivering a virtual address associated with the atomic instruction and an atomic load signal to a translation lookaside buffer containing at least one virtual to physical address translation in response to determining that the atomic instruction is the oldest instruction in the queue; and

forcing a miss in the translation lookaside buffer in response to receiving the atomic load signal.

11. A computer readable program storage device, as set forth in claim 10, wherein the translation lookaside buffer includes a first level and a second level translation lookaside buffer and wherein the method further comprises forcing a miss in the translation lookaside buffer further comprises forcing a miss in the first level translation lookaside buffer in response to receiving the atomic load signal.

12. A computer readable program storage device, as set forth in claim 11, the method further comprising inspecting the second level translation lookaside buffer for the virtual to physical address translation corresponding to the atomic instruction in response to the forced miss in the first level translation lookaside buffer.

13. A computer readable program storage device, as set forth in claim 12, the method further comprising sending the virtual to physical address translation corresponding to the atomic instruction from the second level translation lookaside buffer to the first level translation lookaside buffer in response to detecting the virtual to physical address translation corresponding to the atomic instruction in the second level translation lookaside buffer.

14. A computer readable program storage device, as set forth in claim 13, the method further comprising the second level translation lookaside buffer sending a miss signal in response to the detecting that the virtual to physical address translation corresponding to the atomic instruction is absent from the second level translation lookaside buffer, and wherein a tablewalker is adapted to retrieve the virtual to physical address translation corresponding to the atomic instruction from memory in response to receiving the miss signal from the second level translation lookaside buffer.

15. A computer readable program storage device, as set forth in claim 14, the method further comprising inserting the virtual to physical address translation corresponding to the atomic instruction retrieved from memory into the first and second level translation lookaside buffers.

16. A computer readable program storage device, as set forth in claim 10, the method further comprising removing the virtual to physical address translation that corresponds to the atomic instruction from the first level translation lookaside buffer in response to receiving the atomic load signal.

17. An apparatus, comprising:

a queue adapted to;

identify an atomic instruction within a plurality of load instructions to be executed;

prevent execution of the atomic instruction until it is the oldest instruction in the queue; and

send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue; and

a translation lookaside buffer adapted for maintaining at least one virtual to physical address translation, the translation lookaside buffer being adapted to force a miss in the translation lookaside buffer in response to receiving the atomic load signal.

18. An apparatus, as set forth in claim 17, wherein the translation lookaside buffer includes a first level and a second level translation lookaside buffer and wherein the forced miss occurs in the first level translation lookaside buffer in response to receiving the atomic load signal.

19. An apparatus, as set forth in claim 18, further comprising the second level translation lookaside buffer being adapted to inspect for the virtual to physical address translation corresponding to the atomic instruction in response to the forced miss in the first level translation lookaside buffer.

20. An apparatus, as set forth in claim 19, further comprising the second level translation lookaside buffer being adapted to send the virtual to physical address translation corresponding to the atomic instruction to the first level translation lookaside buffer in response to detecting the virtual to physical address translation corresponding to the atomic instruction in the second level translation lookaside buffer.

21. A method, as set forth in claim 20, wherein the second level translation lookaside buffer is adapted to send a miss signal in response to the detecting that the virtual to physical address translation corresponding to the atomic instruction is absent from the second level translation lookaside buffer, and further comprising a tablewalker being adapted to retrieve the virtual to physical address translation corresponding to the atomic instruction from memory in response to receiving the miss signal from the second level translation lookaside buffer.

22. An apparatus, as set forth in claim 21, further comprising the first and second level translation lookaside buffers being adapted to insert the virtual to physical address translation corresponding to the atomic instruction retrieved from memory into the first and second level translation lookaside buffers.

23. A method, as set forth in claim 17, further comprising the first level translation lookaside buffer being adapted to remove the virtual to physical address translation that corresponds to the atomic instruction from the first level translation lookaside buffer in response to receiving the atomic load signal.

24. A computer readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create an apparatus, comprising:

a queue adapted to;

identify an atomic instruction within a plurality of load instructions to be executed;

prevent execution of the atomic instruction until it is the oldest instruction in the queue; and

send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue; and

a translation lookaside buffer adapted for maintaining at least one virtual to physical address translation, the translation lookaside buffer being adapted to force a miss in the translation lookaside buffer in response to receiving the atomic load signal.