Microprocessor comprising signature means for detecting an attack by error injection

• US 8,341,475 B2
• Filed: 02/01/2011
• Issued: 12/25/2012
• Est. Priority Date: 04/21/2004
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Bancel, Frédéric, Berard, Nicolas
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US13/019,143
• Publication Number:
  US 20110126065A1
• Time in Patent Office: 693 Days
• Field of Search: 714/732
• US Class Current: 714/732
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information

Abstract

A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. Current cumulative signatures are produced using deterministic address, control or data logic signals involved in the execution of the sequence and taken off at various points of the integrated circuit. A final cumulative signature is compared with an expected signature and an error signal is produced if the two signatures are not identical. Particularly useful to secure integrated circuits for smart cards.

Claims

1. A method, comprising:

executing a sequence of instructions on an integrated circuit;

monitoring execution of the sequence of instructions, the monitoring including,

selecting, from a plurality of deterministic and nondeterministic logic signals on the integrated circuit, sets of deterministic logic signals involved in execution of the sequence of instructions;

producing current cumulative signatures based on current selected sets of deterministic logic signals and previous cumulative signatures; and

comparing a final current cumulative signature produced during monitoring of execution of the sequence of instructions with an expected signature; and

generating a signal indicative of an injected error based on the comparing, wherein the monitoring and generating are performed by the integrated circuit.

2. The method of claim 1 wherein:

the sequence of instructions is executed on a central processing unit of the integrated circuit;

a clock signal of the central processing unit paces the producing of current cumulative signatures; and

a current cumulative signature is produced at each clock cycle of the central processing unit during execution of the sequence of instructions.

3. The method of claim 1 wherein each set of selected deterministic logic signals comprises at least part of one of:

an address corresponding to a peripheral element of a central processing unit of the integrated circuit;

a signal for controlling the peripheral element;

a signal indicative of an operation in progress;

a signal indicative of data forming operands; and

a signal indicative of data forming instruction codes.

4. The method of claim 1 wherein a signal is excluded from a selected set of deterministic signals if it is not deterministic during a clock cycle in which the set is selected.

5. The method of claim 1 wherein the current cumulative signatures are produced by a hard-wired logic signature calculation module comprising parallel inputs linked to a plurality of points of the integrated circuit through which deterministic and non-deterministic logic signals pass, and wherein the selecting comprises inhibiting inputs of the signature calculation circuit when corresponding logic signals are not deterministic.

6. The method of claim 5 wherein inputs of the signature calculation module are inhibited by a configurable hard-wired logic masking circuit.

7. The method of claim 5 wherein the inputs of the signature calculation module are connected to a data bus, to an address bus, and to a control bus conveying signals for controlling peripheral elements of a central processing unit of the integrated circuit.

8. The method of claim 1 wherein the producing current cumulative signatures includes using a linear feedback shift register.

9. The method of claim 1 wherein the generating the signal indicative of an injected error comprises:

during the execution of the sequence of instructions, producing an error signal having an active value by default while a current cumulative signature is different from the expected signature;

masking the error signal for a determined time interval corresponding substantially to a presumed duration of execution of the sequence of instructions; and

unconditionally lifting the masking of the error signal when the determined time interval expires.

10. An integrated circuit, comprising:

a processor configured to execute a sequence of instructions;

a signature production module configured to;

select, from a plurality of deterministic and nondeterministic logic signals on the integrated circuit, sets of deterministic logic signals involved in execution of the sequence of instructions; and

produce current cumulative signatures based on sets of deterministic logic signals; and

an error injection detection module coupled to the signature production module and configured to produce a signal based on a comparison of a current cumulative signature with an expected final cumulative signature.

11. The integrated circuit of claim 10, further comprising:

a data bus;

a control bus; and

an address bus, wherein the signature production module includes a signal masking module configured to mask non-deterministic signals on the data bus, the control bus and the address bus.

12. The integrated circuit of claim 10, further comprising a peripheral device wherein the signature production circuit is configured to select deterministic signals related to the peripheral device.

13. The integrated circuit of claim 12 wherein the deterministic signals related to the peripheral device include at least one of:

an address corresponding to the peripheral device; and

a control signal related to the peripheral device.

14. The integrated circuit of claim 12 wherein the peripheral device is a cryptographic calculation module.

15. The integrated circuit of claim 10 wherein the error injection detection module is configured to compare the current cumulative signature with the expected final cumulative signature after execution of the sequence of instructions is complete.

16. The integrated circuit of claim 10 wherein the error injection detection module is configured to compare the current cumulative signature with the expected final signature during execution of the sequence of instructions.

17. The integrated circuit of claim 10 wherein the error injection detection module comprises:

a comparator; and

an error masking module coupled to the comparator and configured to mask an output of the comparator when the current cumulative signature is not expected to be equivalent to the expected final cumulative signature.

18. The integrated circuit of claim 10, further comprising:

an error management module coupled to the error injection detection module.

19. A non-transitory computer-readable medium containing instructions which when executed configure an integrated circuit to perform a method, the method comprising:

executing a sequence of instructions;

monitoring execution of the sequence of instructions, the monitoring including,

selecting, from a plurality of deterministic and nondeterministic logic signals on the integrated circuit, sets of deterministic logic signals involved in execution of the sequence of instructions;

producing current cumulative signatures based on current selected sets of deterministic logic signals and previous cumulative signatures; and

comparing a final current cumulative signature produced during monitoring of execution of the sequence of instructions with an expected signature; and

generating a signal indicative of an injected error based on the comparing.

20. The non-transitory computer-readable medium of claim 19 wherein the selected sets of deterministic logic signals comprise at least part of an address signal, a control signal and a data logic signal.

21. The non-transitory computer-readable medium of claim 19 wherein the each of the plurality of signals is deterministic during at least one cycle of execution of the sequence of instructions.

22. A system comprising:

a smart card; and

an electronic device coupled to the smart card, wherein the system includes an integrated circuit, the integrated circuit having;

a processor configured to execute a sequence of instructions;

a signature production module configured to;

select, from a plurality of deterministic and nondeterministic logic signals on the integrated circuit, sets of deterministic logic signals involved in execution of the sequence of instructions; and

produce current cumulative signatures based on sets of deterministic logic signals; and

an error injection detection module coupled to the signature production module and configured to produce a signal based on a comparison of a current cumulative signature with an expected final cumulative signature.

23. The system of claim 22 wherein the integrated circuit is including in the smart card.

24. The system of claim 22 wherein the integrated circuit is included in the electronic device.

25. The system of claim 22 wherein the electronic device is a set top box.

26. The system of claim 22 wherein the electronic device is a cellular device.

27. The system of claim 22 wherein the error injection detection module comprises:

a comparator; and

an error masking module coupled to the comparator and configured to mask an output of the comparator when the current cumulative signature is not expected to be equivalent to the expected final cumulative signature.

28. The system of claim 22 wherein the integrated circuit comprises:

an error management module coupled to the error injection detection module.