Embedded trace macrocell for enhanced digital signal processor debugging operations

• US 8,341,604 B2
• Filed: 11/15/2006
• Issued: 12/25/2012
• Est. Priority Date: 11/15/2006
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Codrescu, Lucian, Anderson, William C., Venkumahanti, Suresh, Giannini, Louis Achille, Pyla, Manojkumar, Chen, Xufeng
• Primary Examiner(s): DAO, THUY CHAN
• Application Number:
  US11/560,339
• Publication Number:
  US 20080115115A1
• Time in Patent Office: 2,232 Days
• Field of Search: None
• US Class Current: 717/129
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 9/3005 to perform operations for flow control

Abstract

Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution. The present disclosure controls aspects of the non-intrusive debugging process in response to at least one breakpoint.

Claims

1. A method for software instruction debugging by capturing real-time information relating to software execution flow in a digital signal processor, comprising:

operating a non-intrusive debugging process within a debugging mechanism of the digital signal processor, the debugging mechanism associated with a core processor of the digital signal processor, wherein the digital signal processor includes a plurality of threads;

non-intrusively monitoring software execution in real-time for predetermined aspects of software execution associated with the core processor;

recording selectable aspects of the non-intrusively monitored software execution;

generating at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution, wherein the at least one breakpoint is generated from at least one of a plurality of breakpoint triggers that includes a hardware breakpoint trigger and an embedded trace macrocell breakpoint trigger;

controlling aspects of the non-intrusive debugging process in response to the at least one breakpoint; and

generating by the debugging mechanism a thread match signal based on at least one address space identifier of at least one of the plurality of threads, wherein the thread match signal matches the at least one of the plurality of threads to the at least one breakpoint.

2. The method of claim 1, further comprising generating at least one record in response to a predetermined set of profiling counts.

3. The method of claim 1, further comprising non-intrusively monitoring the software execution of a selectable number of threads of the digital signal processor.

4. The method of claim 1, further comprising generating in response to a program counter value a trigger for initiating the non-intrusive debugging process.

5. The method of claim 1, further comprising generating a trigger for initiating the non-intrusive debugging process in response to a load/store address used in the software execution.

6. The method of claim 1, further comprising generating a plurality of records in response to a sequence of events occurring in the software execution.

7. The method of claim 1, further comprising generating at least one record in response to an external event occurring in relation to the software execution.

8. The method of claim 1, further comprising programming operation of the non-intrusive monitoring and the recording using a JTAG interface.

9. The method of claim 1, further comprising generating a packet stream of records derived from the recording for transmitting to a recording medium.

10. The method of claim 1, further comprising generating a packet stream of records derived from the recording for transmitting to an embedded trace buffer recording medium.

11. The method of claim 1, wherein the thread match signal is further based on a thread identifier of the at least one thread and a thread number of the at least one thread.

12. The method of claim 1, wherein a first of the plurality of threads operates in a debug mode independently of a mode of operation of other threads of the plurality of threads.

13. The method of claim 1, wherein the at least one of a plurality of breakpoint triggers includes a second hardware breakpoint trigger.

14. The method of claim 1, wherein the at least one of a plurality of breakpoint triggers includes a JTAG breakpoint trigger.

15. A digital signal processor debugging system for operation in association with a digital signal processor and including the ability to capture real-time information relating to software execution flow in a processor, comprising:

a debugging mechanism of the digital signal processor, the debugging mechanism associated with a core processor of the digital signal processor and operating a non-intrusive debugging process, wherein the digital signal processor includes a plurality of threads;

an embedded trace macrocell for non-intrusively monitoring software execution in real-time for predetermined aspects of software execution associated with the core processor;

recording instructions and associated circuitry for the embedded trace macrocell for recording selectable aspects of the non-intrusively monitored software execution;

a breakpoint generating instruction associated with the debugging mechanism and the embedded trace macrocell for generating at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution, wherein the at least one breakpoint is generated from at least one of a plurality of breakpoint triggers that includes a hardware breakpoint trigger and an embedded trace macrocell breakpoint trigger; and

control instructions associated with the debugging mechanism for initiating the non-intrusive debugging process in response to the at least one breakpoint,

wherein the debugging mechanism is configured to generate a thread match signal based on at least one address space identifier of at least one of the plurality of threads and wherein the thread match signal matches the at least one of the plurality of threads to the at least one breakpoint.

16. The digital signal processor debugging system of claim 15, wherein the embedded trace macrocell generates at least one record in response to a predetermined set of profiling counts.

17. The digital signal processor debugging system of claim 15, wherein the plurality of threads comprises a selectable number of threads.

18. The digital signal processor debugging system of claim 15, wherein the debugging mechanism generates a trigger for initiating the non-intrusive debugging process in response to a program counter value.

19. The digital signal processor debugging system of claim 15, wherein the debugging mechanism generates a trigger for initiating the non-intrusive debugging process in response to a load/store address used in the software execution.

20. The digital signal processor debugging system of claim 15, wherein the embedded trace macrocell generates a plurality of records in response to a sequence of events occurring in the software execution.

21. The digital signal processor debugging system of claim 15, wherein the embedded trace macrocell generates at least one record in response to an external event occurring in relation to the software execution.

22. The digital signal processor debugging system of claim 15, further comprising a JTAG interface for programming the operation of the non-intrusive monitoring and for programming the recording instructions and associated circuitry.

23. The digital signal processor debugging system of claim 15, further comprising a packet stream of records derived from the recording instructions and associated circuitry to transmit to a recording medium.

24. The digital signal processor debugging system of claim 15, further comprising an embedded trace buffer for storing a packet stream of records derived from use of the recording instructions and associated circuitry.

25. The digital signal processor debugging system of claim 15, wherein the debugging mechanism includes at least one address comparator configured to output a signal based on an address matching a value, the value corresponding to the hardware breakpoint trigger.

26. The digital signal processor debugging system of claim 15, wherein the debugging mechanism includes a register, and wherein the debugging mechanism is further configured to cause the digital signal processor to enter a debugging mode at least partially in response to a program counter value of the digital signal processor matching a value indicated by the register.

27. The digital signal processor debugging system of claim 15, wherein the debugging mechanism includes an in-silicon debugging system (ISDB) that includes a Joint Test Action Group (JTAG) interface.

28. The digital signal processor debugging system of claim 15, wherein the debugging mechanism includes at least one of a hardware breakpoint trigger circuit associated with the hardware breakpoint trigger, an embedded trace macrocell breakpoint trigger circuit associated with the embedded trace macrocell breakpoint trigger, a software breakpoint trigger circuit associated with a software breakpoint trigger, and a Joint Test Action Group (JTAG) breakpoint trigger circuit associated with a JTAG breakpoint trigger, and wherein the plurality of breakpoint triggers further includes the software breakpoint trigger and the JTAG breakpoint trigger.

29. A digital signal processor for operation in support of a personal electronics device, the digital signal processor comprising:

means for operating a non-intrusive debugging process within a debugging mechanism of the digital signal processor, the debugging mechanism associated with a core processing process operating on a core processor of the digital signal processor, wherein the digital signal processor includes a plurality of threads;

means for non-intrusively monitoring software execution in real-time for predetermined aspects of software execution associated with the core processing process and occurring in real-time on the core processor;

means for recording selectable aspects of the non-intrusively monitored software execution;

means for generating at least one breakpoint in response to events arising within the means for recording selectable aspects of the non-intrusively monitored software execution, wherein the at least one breakpoint is generated from at least one of a plurality of breakpoint triggers that includes a hardware breakpoint trigger and an embedded trace macrocell breakpoint trigger;

means for controlling aspects of the non-intrusive debugging process in response to the at least one breakpoint; and

means for generating a thread match signal based on at least one address space identifier of at least one of the plurality of threads, wherein the thread match signal matches the at least one of the plurality of threads to the at least one breakpoint.

30. The digital signal processor of claim 29, further comprising means for generating at least one record in response to a predetermined set of profiling counts.

31. The digital signal processor of claim 29, further comprising means for selecting a number of threads of the digital signal processor.

32. The digital signal processor of claim 29, further comprising means for generating a trigger for initiating the non-intrusive debugging process in response to a program counter value, in response to a load/store address used in the software execution, or any combination thereof.

33. The digital signal processor of claim 29, further comprising means for generating a plurality of records in response to a sequence of events occurring in the software execution, in response to an external event occurring in relation to the software execution, or any combination thereof.

34. The digital signal processor of claim 29, further comprising means for programming the operation of the non-intrusive monitoring and the means for recording using a JTAG interface.

35. The digital signal processor of claim 29, further comprising means for generating a packet stream of records derived from the means for recording to transmit to a recording medium, to an embedded trace buffer recording medium, or any combination thereof.

36. A non-transitory computer usable medium, comprising:

computer readable program code means for operating a non-intrusive debugging process within a debugging mechanism of a multi-threaded digital signal processor, the debugging mechanism associated with a core processor;

computer readable program code means for non-intrusively monitoring software execution in real-time for predetermined aspects of software execution associated with the core processor and occurring in real-time on the digital signal processor;

computer readable program code means for recording selectable aspects of the non-intrusively monitored software execution;

computer readable program code means for generating at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution, wherein the at least one breakpoint is generated from at least one of a plurality of breakpoint triggers that includes a hardware breakpoint trigger and an embedded trace macrocell breakpoint trigger;

computer readable program code means for controlling aspects of the non-intrusive debugging process in response to the at least one breakpoint;

computer readable program code means for selecting at least one thread from a plurality of threads of the multi-threaded digital signal processor; and

computer readable program code means for generating a thread match signal based on at least one address space identifier of at least one of the plurality of threads, wherein the thread match signal matches the at least one of the plurality of threads to the at least one breakpoint.

37. The non-transitory computer usable medium of claim 36, further comprising computer readable program code means for generating a packet stream of records derived from the computer readable program code means for recording to transmit to an embedded trace buffer recording medium.