Recessed gate channel with low Vt corner

• US 8,343,836 B2
• Filed: 02/01/2012
• Issued: 01/01/2013
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Anderson, Brent A., Bryant, Andres, Nowak, Edward J.
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): HENRY, CALEB E
• Application Number:
  US13/363,944
• Publication Number:
  US 20120190156A1
• Time in Patent Office: 335 Days
• Field of Search: 438/175, 438/193, 438/270, 438/282
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region.

Claims

1. A method of forming a recessed gate FET comprising the steps of:

providing a semiconductor substrate having an upper doped portion and a lower doped portion beneath a substrate surface;

forming a trench in said substrate to define a gate electrode and a channel region surrounding said gate electrode, a bottom corner of said trench extending into said lower doped portion of said substrate;

lining sidewalls and bottom portions of said trench with dielectric material layer;

filling said trench with a material to form a gate conductor;

recessing said gate conductor below a substrate surface to define an opening at an upper portion of said trench;

optionally forming doped pocket regions at either side of and abutting said gate electrode, each doped pocket region extending into said channel region;

providing a dielectric cap in said formed opening; and

forming source and drain diffusion regions at either side of said gate electrode at said substrate surface that contact respective formed doped pocket regions, wherein a bottom portion of said trench is formed in said lower doped portion of said substrate, said recessed gate FET thereby exhibiting improved suppression of short channel effects.

2. The method of forming a recessed gate FET of claim 1, where said bottom portion of said trench exhibits lower threshold voltage than said upper portion of said trench by reducing doping concentration of dopant material in said lower portion of said substrate than in said upper portion.

3. The method of forming a recessed gate FET as claimed in claim 1, wherein prior to said providing a dielectric cap in said formed opening, a step of:

forming extension regions of highly doped material adjacent an upper portion of said gate electrode within said optionally formed doped pocket regions at either side of said gate electrode to provide a low resistance path to said channel region from a respective formed source diffusion and drain diffusion region.

4. The method of forming a recessed gate FET as claimed in claim 1, wherein said gate electrode of conductive material is recessed by an amount relative to said source and drain diffusion regions formed at either side of said gate electrode to reduce overlap capacitance between said gate electrode and said gate and source and drain diffusions.

5. The method of forming a recessed gate FET as claimed in claim 2, wherein said recessed gate FET exhibits improved threshold voltage (Vt) characteristics at corners of said trench bottom formed in said lower doped portion of said substrate.

6. The method of forming a recessed gate FET as claimed in claim 2, wherein said semiconductor substrate is an Silicon on Insulator (SOI) structure having a buried layer of insulating dielectric material, said gate trench being formed to extend to a depth above said buried layer such that a thin substrate portion remains between said buried layer and said gate trench bottom portion, said thin substrate portion being slightly doped or fully depleted.

7. The method of forming a recessed gate FET as claimed in claim 1, wherein said gate conductor material is polysilicon, and prior to providing said dielectric cap in said formed opening, forming a metal silicide contact in said gate electrode, said metal silicide contact forming comprising:

forming spacers at sidewalls of said formed opening;

performing an etch process to extend said opening in said polysilicon gate conductor material that is aligned with an opening defined by said spacers;

filling said opening in said polysilicon gate conductor with a metal material; and

annealing to form said metal silicide contact for said gate electrode.

8. The method of forming a recessed gate FET as claimed in claim 7, further comprising:

forming metal silicide contact regions on top of each source and drain diffusion region.

9. The method of forming a recessed gate FET as claimed in claim 1, wherein said step of optionally forming doped pocket regions at either side of and abutting said gate electrode comprises:

performing an angled ion implantation process at sufficient energies; and

concentrations to form said doped packet regions at either side of said gate electrode.

10. The method of forming a recessed gate FET as claimed in claim 1, wherein said step of forming extension regions of highly doped material adjacent an upper portion of said gate electrode comprises:

providing highly doped material in said formed opening; and

outdiffusing dopant material to form said extensions adjacent an upper portion of said gate electrode.

11. A method of forming a recessed gate FET comprising the steps of:

providing a semiconductor substrate having an upper doped portion and a lower doped portion beneath a substrate surface;

forming a trench in said substrate to define a gate electrode and a channel region surrounding said gate electrode, a bottom corner of said trench extending into said lower doped portion of said substrate;

lining sidewalls and bottom portions of said trench with dielectric material layer;

filling said trench with a material to form a gate conductor;

recessing said gate conductor below a substrate surface to define an opening at an upper portion of said trench;

forming doped pocket regions at either side of and abutting said gate electrode, each doped pocket region extending into said channel region;

forming extension regions of highly doped material adjacent an upper portion of said gate electrode within said formed doped pocket regions at either side of said gate electrode;

providing a dielectric cap in said formed opening; and

forming source and drain diffusion regions at either side of said gate electrode at said substrate surface that contact respective extension regions, said extension regions providing a low resistance path from said source and drain diffusion regions to said channel region, wherein a bottom portion of said trench is formed in said lower doped portion of said substrate, said recessed gate FET thereby exhibiting improved suppression of short channel effects.

12. The method of forming a recessed gate FET of claim 11, where said bottom portion of said trench exhibits lower threshold voltage than said upper portion of said trench by reducing doping concentration of dopant material in said lower portion of said substrate than in said upper portion.

13. The method of forming a recessed gate FET as claimed in claim 11, wherein said gate conductor is recessed by an amount relative to said source and drain diffusion regions formed at either side of said gate electrode to reduce overlap capacitance between said gate electrode and said gate and source and drain diffusions.

14. The method of forming a recessed gate FET as claimed in claim 12, wherein said recessed gate FET exhibits improved threshold voltage (Vt) characteristics at corners of said trench bottom formed in said lower doped portion of said substrate.

15. The method of forming a recessed gate FET as claimed in claim 11, wherein said semiconductor substrate is an Silicon on Insulator (SOI) structure having a buried layer of insulating dielectric material, said gate trench being formed to extend to a depth above said buried layer such that a thin substrate portion remains between said buried layer and said gate trench bottom portion, said thin substrate portion being slightly doped or fully depleted.

16. A method of forming a recessed gate FET comprising the steps of:

providing a semiconductor substrate having an upper doped portion and a lower doped portion beneath a substrate surface;

providing a thin dielectric layer atop an upper surface of said substrate;

forming a trench in said substrate to define a gate electrode and a channel region surrounding said gate electrode, a bottom corner of said trench extending into said lower doped portion of said substrate;

filling said trench with sacrificial dielectric material;

recessing a portion of said sacrificial dielectric material to a depth below a substrate surface to form an opening in an upper trench portion of said gate electrode;

forming extension regions of highly doped material adjacent said upper trench portion of said gate electrode;

removing said sacrificial dielectric material from said trench;

thermally growing a gate dielectric material layer that lines said sidewall and bottom of said trench;

filling said dielectric material lined trench with a conductor material to form a gate conductor;

recessing said gate conductor below a substrate surface to define an opening at an upper portion of said trench;

providing a dielectric cap in said formed opening; and

forming source and drain diffusion regions at either side of said gate electrode at said substrate surface that contact respective extension regions, said extension regions providing a low resistance path from respective source and drain diffusions to said channel region, wherein a bottom portion of said trench is formed in said lower doped portion of said substrate, said recessed gate FET thereby exhibiting improved suppression of short channel effects.

17. The method of forming a recessed gate FET of claim 16, where said bottom portion of said trench exhibits lower threshold voltage than said upper portion of said trench by reducing doping concentration of dopant material in said lower portion of said substrate than in said upper portion.

18. The method of forming a recessed gate FET as claimed in claim 16, wherein said forming extension regions of highly doped material adjacent said upper trench portion of said gate electrode comprises:

providing highly doped material in said formed opening; and

outdiffusing dopant material to form said extensions adjacent an upper portion of said gate electrode.

19. The method of forming a recessed gate FET as claimed in claim 16, wherein said thermally grown gate dielectric material layer comprises an oxide, said oxide being grown at a higher thermal growth rate at said upper trench portion at locations corresponding to where said highly doped extension regions are formed as compared to a thermal growth rate at a lower trench portion, said thermally grown gate dielectric material layer including self-aligned oxide spacers at said upper trench portion.

20. The method of forming a recessed gate FET as claimed in claim 16, wherein said gate conductor material is recessed by an amount relative to said source and drain diffusion regions formed at either side of said gate electrode to reduce overlap capacitance between said gate electrode and said gate and source and drain diffusions.