Blocking dielectric engineered charge trapping memory cell with high speed erase

• US 8,343,840 B2
• Filed: 04/19/2010
• Issued: 01/01/2013
• Est. Priority Date: 08/09/2007
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lai, Sheng-Chih, Lue, Hang-Ting, Liao, Chien-Wei
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Chen, Yu
• Application Number:
  US12/763,006
• Publication Number:
  US 20100193859A1
• Time in Patent Office: 988 Days
• Field of Search: 257324-326, 257/E21.423, 257/E29.309, 438/287
• US Class Current: 438/287
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

Claims

1. A method for manufacturing a charge trapping memory comprising:

defining a semiconductor body including a channel region on the semiconductor body, the channel region having a channel surface;

defining a gate;

forming a dielectric stack between the channel surface and the gate, including forming a tunneling dielectric layer;

forming a charge trapping dielectric layer; and

forming a blocking dielectric layer, the blocking dielectric layer consisting of an aluminum doped silicon dioxide having a dielectric constant κ

between 4.5 and 7.

2. The method of claim 1, wherein the tunneling dielectric layer comprises a combination of materials arranged to establish a valence band energy level at an interface between the tunneling dielectric layer and the channel surface, and an increase in the valence band energy level at a first offset from the channel surface and an increase in conduction band energy level at a second offset more than 2 nm from the channel surface relative to a conduction band energy level between the first offset and the second offset.

3. The method of claim 1, wherein the gate comprises a metal or a metal compound.

4. The method of claim 1, wherein the gate comprises n+ doped or p+ doped polysilicon.

5. The method of claim 1, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness less than 20 Å

, a low barrier height layer on the first silicon oxide layer, having a hole tunneling barrier height less than 3 eV, and an isolation layer isolating the low barrier height layer from the charge trapping dielectric layer.

6. The method of claim 5, wherein the thickness of the first silicon oxide layer is 15 Å

or less.

7. The method of claim 1, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness of 20 Å

or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 30 Å

or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å

or less.

8. A method for manufacturing a charge trapping memory comprising:

defining a semiconductor body including a channel region on the semiconductor body, the channel region having a channel surface;

defining a gate;

forming a dielectric stack between the channel surface and the gate, including forming a tunneling dielectric layer;

forming a charge trapping dielectric layer; and

forming a blocking dielectric layer, the blocking dielectric layer comprising an aluminum doped silicon dioxide having a dielectric constant κ

between 4.5 and 7, wherein an electron barrier height between the gate and the blocking dielectric layer is more than 3 eV.

9. The method of claim 8, wherein the aluminum doped silicon dioxide has a concentration of aluminum between 1 and 10 atomic percent relative to the sum of aluminum and silicon atoms.

10. A charge trapping memory comprising an array of memory cells, respective memory cells in the array including:

a semiconductor body including a channel having a channel surface;

a dielectric stack between a gate and the channel surface;

the dielectric stack comprising;

a tunneling dielectric layer;

a charge trapping dielectric layer on the tunneling dielectric layer;

a blocking dielectric layer on the charge trapping layer, the blocking dielectric layer consisting of an aluminum doped silicon oxide having a dielectric constant κ

between 4.5 and 7.

11. The memory of claim 10, wherein the tunneling dielectric layer comprises a combination of materials arranged to establish a valence band energy level at an interface between the tunneling dielectric layer and the channel surface, and an increase in the valence band energy level at a first offset from the channel surface and an increase in conduction band energy level at a second offset more than 2 nm from the channel surface relative to a conduction band energy level between the first offset and the second offset.

12. The memory of claim 11, wherein the aluminum doped silicon dioxide has a concentration of aluminum between 1 and 10 atomic percent relative to the sum of aluminum and silicon atoms, and an electron barrier height between the gate and the blocking dielectric layer of more than 3 eV.