Method and structure for dividing a substrate into individual devices

• US 8,343,852 B2
• Filed: 04/27/2011
• Issued: 01/01/2013
• Est. Priority Date: 10/01/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Li, Minhua, Wang, Qi, Sim, Gordon, Reynolds, Matthew, Kim, Suku, Murphy, James J., Yilmaz, Hamza
• Primary Examiner(s): Mandala, Michelle
• Application Number:
  US13/095,584
• Publication Number:
  US 20110201179A1
• Time in Patent Office: 615 Days
• Field of Search: 438/110, 438/118, 438/458, 438/459, 438/462, 438/464, 257/E21.214, 257/E21.237, 257/E21.599
• US Class Current: 438/462
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.

Claims

1. A method for obtaining an individual device from a semiconductor structure that includes a device layer formed on a substrate, the device layer including a plurality of devices separated by respective predefined spacings, the method comprising:

forming a vertically extending structure on a backside surface of the substrate, the vertically extending structure being aligned with the respective predefined spacings of the individual device, the vertically extending structure forming an opening on the backside surface of the substrate that is aligned with the individual device;

forming a metal layer in the opening; and

cutting through the vertically extending structure to separate the individual device from the substrate.

2. The method of claim 1 wherein the metal layer is formed using selective electroplating.

3. The method of claim 1 further comprising:

prior to forming the metal layer, forming a seed layer on a bottom surface of the opening and on a top surface of the vertically extending structure, the seed layer being discontinuous on a sidewall of the opening.

4. The method of claim 3 wherein forming the metal layer comprises:

inducing a plating current through a portion of the seed layer on the bottom surface of the opening.

5. The method of claim 3 wherein the seed layer includes a second metal layer and a diffusion barrier layer.

6. The method of claim 1 wherein the individual device includes a FET structure, the FET structure including:

a source region;

a topside metal layer contacting the source region; and

a drain region in contact with the metal layer in the opening, the metal layer in the opening being thicker than the topside metal layer.

7. The method of claim 1 wherein the respective predefined spacings include respective scribe line regions.

8. The method of claim 7 wherein the vertically extending structure is formed using a backside alignment masking process that aligns the vertically extending structure with the respective scribe line regions of the individual device.

9. A method for separating an individual device from a semiconductor structure that includes a device layer formed on a substrate, the device layer including a plurality of devices separated by respective predefined spacings, the method comprising:

forming a metal layer on a backside surface of the substrate;

using a masking layer, removing a portion of the metal layer so that a corresponding portion of the backside surface of the substrate is exposed, the exposed portion of the backside surface of the substrate being aligned with the respective predefined spacings of the individual device, such that an island of the metal layer that is aligned with the individual device remains on the backside surface of the substrate; and

after removing the portion of the metal layer, cutting the semiconductor structure along the exposed portion of the backside surface of the substrate to separate the individual device.

10. The method of claim 9 wherein the predefined spacings include scribe line regions.

11. The method of claim 9 wherein the metal layer is formed using blanket electroplating.

12. The method of claim 9 further comprising:

prior to forming the metal layer, forming a seed layer on the backside surface of the substrate; and

inducing a plating current through the seed layer to form the metal layer from the seed layer.

13. The method of claim 12 wherein the seed layer includes a second metal layer and a diffusion barrier layer.

14. The method of claim 9 wherein using the masking layer to remove the portion of the metal layer includes using a backside alignment masking process to ensure that the metal layer is not cut when cutting the semiconductor structure to separate the individual device.

15. The method of claim 9 wherein the individual device includes a FET structure, the FET structure including:

a source region;

a topside metal layer contacting the source region; and

a drain region in contact with the metal layer on the backside surface of the substrate, the metal layer on the backside surface of the substrate being thicker than the topside metal layer.