Method for forming gallium nitride devices with conductive regions

• US 8,343,856 B2
• Filed: 11/22/2011
• Issued: 01/01/2013
• Est. Priority Date: 12/02/2005
• Status: Active Grant

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Therrien, Robert J., Johnson, Jerry W., Hanson, Allen W.
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US13/303,075
• Publication Number:
  US 20120070967A1
• Time in Patent Office: 406 Days
• Field of Search: 438/285, 438/478, 438/479, 257/103, 257191-194, 257/E29.089
• US Class Current: 438/479
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/89 using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/351 Thermal stress
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body

Abstract

Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.

Claims

1. A method of forming a semiconductor device structure comprising:

forming a gallium nitride material layer on a substrate;

forming a via that extends through at least a portion of said substrate;

forming a barrier material layer along sidewalls of said via, said barrier material layer not extending outside of said via;

forming a layer comprising an electrically conductive material on a back surface of said substrate to form a semiconductor structure;

heating said semiconductor structure to form a bond between said semiconductor structure and a component.

2. The method of claim 1, wherein said substrate comprises silicon.

3. The method of claim 1, wherein said electrically conductive material comprises aluminum.

4. The method of claim 1, wherein said electrically conductive material includes a first layer portion comprising gold and a second layer portion having a different composition than said first layer portion.

5. The method of claim 4, wherein said second layer portion comprises aluminum.

6. The method of claim 1, further comprising a passivating layer formed over said gallium nitride material region.

7. The method of claim 1, wherein said semiconductor structure is a transistor and further comprises a source electrode, a drain electrode and a gate electrode, wherein said first electrical contact is electrically connected to said source electrode.

8. The method of claim 7, wherein said gate electrode is defined by an electrode-defining layer comprising silicon nitride.

9. The method of claim 1, further comprising a transition layer formed between said substrate and said gallium nitride material region.

10. The method of claim 9, wherein said transition layer is compositionally-graded.

11. The method of claim 9, further comprising a silicon nitride layer formed between said substrate and said transition layer.

12. A method of forming a semiconductor device comprising:

forming a gallium nitride material layer on a silicon substrate;

forming a via that extends through at least a portion of said silicon substrate;

forming a bather material layer along sidewalls of said via, said barrier material layer not extending outside of said via;

forming a layer comprising an electrically conductive material on a back surface of said silicon substrate to form a semiconductor structure;

heating said semiconductor structure to form a liquid eutectic comprising said electrically conductive material and silicon; and

cooling said liquid eutectic to form a bond between said semiconductor structure and a component.

13. The method of claim 12, wherein said electrically conductive material comprises aluminum.

14. The method of claim 12, wherein said electrically conductive material includes a first layer portion comprising gold and a second layer portion having a different composition than said first layer portion.

15. The method of claim 14, wherein said second layer portion comprises aluminum.

16. The method of claim 12, further comprising a passivating layer formed over said gallium nitride material region.

17. The method of claim 12, wherein said semiconductor structure is a transistor and further comprises a source electrode, a drain electrode and a gate electrode, wherein said first electrical contact is electrically connected to said source electrode.

18. The method of claim 17, wherein said gate electrode is defined by an electrode-defining layer comprising silicon nitride.

19. The method of claim 12, further comprising a transition layer formed between said silicon substrate and said gallium nitride material region.

20. The method of claim 19, further comprising a silicon nitride layer formed between said silicon substrate and said transition layer.