DRAM with schottky barrier FET and MIM trench capacitor

• US 8,343,864 B2
• Filed: 03/28/2011
• Issued: 01/01/2013
• Est. Priority Date: 03/28/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Goyal, Puneet, Ho, Herbert Lei, Jana, Pradeep, Liu, Jin
• Primary Examiner(s): Reames, Matthew
• Assistant Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US13/073,103
• Publication Number:
  US 20120248522A1
• Time in Patent Office: 645 Days
• Field of Search: 257/296, 257/301, 257/E29.346, 257/454, 257/471, 257/485, 438/243, 438/246, 438/387, 438/570, 438/581, 438/583
• US Class Current: 438/583
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor

Abstract

A semiconductor circuit and method of fabrication is disclosed. In one embodiment, the semiconductor circuit comprises a metal-insulator-metal trench capacitor in a silicon substrate. A field effect transistor is disposed on the silicon substrate adjacent to the metal-insulator-metal trench capacitor, and a silicide region is disposed between the field effect transistor and the metal-insulator-metal trench capacitor. Electrical connectivity between the transistor and capacitor is achieved without the need for a buried strap.

Claims

1. A method of fabricating a semiconductor circuit comprising:

forming a metal-insulator-metal trench capacitor in a silicon substrate;

forming a field effect transistor on the silicon substrate adjacent to the metal-insulator-metal trench capacitor; and

forming a Schottky Barrier Silicided Source region and a Schottky Barrier Silicided Drain region between the field effect transistor and the metal-insulator-metal trench capacitor wherein one of the Schottky Barrier Silicided Source region and the Schottky Barrier Silicided Drain region is in direct physical contact with the metal-insulator-metal trench capacitor.

2. The method of claim 1, wherein forming a metal-insulator-metal trench capacitor in a silicon substrate comprises:

forming a layer stack on the silicon substrate;

forming a trench in the silicon substrate, wherein the trench also traverses the layer stack;

forming a bottom electrode in the trench;

depositing a dielectric layer in contact with the bottom electrode;

forming a top electrode, wherein the dielectric layer is disposed between the bottom electrode and the top electrode.

3. The method of claim 2, wherein forming a layer stack on the silicon substrate comprises:

depositing a buried oxide layer on the silicon substrate;

depositing a silicon-on-insulator layer on the buried oxide layer;

depositing a SiON layer on the silicon-on-insulator layer; and

depositing a high density plasma oxide layer on the silicon-on-insulator layer.

4. The method of claim 3, wherein depositing a buried oxide layer on the silicon substrate comprises depositing a buried oxide layer having a thickness ranging from about 1050 angstroms to about 1750 angstroms.

5. The method of claim 3, wherein depositing a high density plasma oxide layer comprises depositing a high density plasma oxide layer having a thickness ranging from about 2650 angstroms to about 3350 angstroms.

6. The method of claim 2, wherein forming a bottom electrode in the trench comprises depositing a metal via atomic layer deposition.

7. The method of claim 6, wherein depositing a metal via atomic layer deposition comprises depositing a metal from the group consisting of tungsten, cobalt, and nickel.

8. The method of claim 2, wherein depositing a dielectric layer on the bottom electrode comprises depositing a layer of hafnium oxide.

9. The method of claim 8, wherein depositing a layer of hafnium oxide comprises depositing a layer of silicon doped hafnium oxide.

10. The method of claim 2, wherein forming a top electrode comprises depositing a metal selected from the group consisting of tungsten and titanium.

11. A method of forming a semiconductor circuit comprising:

depositing a buried oxide layer on a silicon substrate;

depositing a silicon-on-insulator layer on the buried oxide layer;

depositing a SiON layer on the silicon-on-insulator layer;

depositing a high density plasma oxide layer on the SiON layer;

forming a trench in the silicon substrate;

depositing a first metal in the trench;

depositing a dielectric layer within the trench;

depositing a second metal within the trench;

planarizing the second metal to the level of the SiON layer;

removing a portion of the second metal, whereby the second metal is recessed to a level below the top of the silicon-on-insulator layer; and

forming a silicided Schottky barrier region disposed on the silicon substrate such that it is in direct physical contact with the second metal in the trench.

12. The method of claim 11, further comprising depositing a trench-top oxide on the second metal.

13. The method of claim 12, further comprising forming an STI trench, wherein the STI trench traverses the silicon-on-insulator layer.

14. The method of claim 13, further comprising filling the STI trench with an STI oxide.

15. The method of claim 14, further comprising planarizing the trench-top oxide and the STI oxide to the level of the top of the silicon-on-insulator layer.

16. A semiconductor circuit comprising:

a silicon substrate;

a metal-insulator-metal trench capacitor formed in the silicon substrate, the metal-insulator-metal trench capacitor comprising a first electrode, a second electrode, and a dielectric layer disposed in between the first electrode and the second electrode;

a field effect transistor disposed on the silicon substrate adjacent to the metal-insulator-metal trench capacitor; and

a silicided Schottky Barrier region disposed on the silicon substrate such that it is in direct physical contact with the metal-insulator-metal trench capacitor to and the field effect transistor.

17. The semiconductor circuit of claim 16, further comprising an oxide layer disposed on the second electrode.

18. The semiconductor circuit of claim 17, wherein the first electrode is comprised of a metal selected from the group consisting of tungsten, cobalt, and nickel.

19. The semiconductor circuit of claim 18, wherein the second electrode is comprised of a metal selected from the group consisting of tungsten and titanium.

20. The semiconductor circuit of claim 18, wherein the dielectric layer is comprised of hafnium oxide.