Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning

• US 8,343,871 B2
• Filed: 03/04/2010
• Issued: 01/01/2013
• Est. Priority Date: 12/31/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Inotera Memories Incorporated (Micron Technology, Inc.)
• Inventors: Shih, Tah-Te, Lee, Chung-Yuan
• Primary Examiner(s): Deo, Duy
• Assistant Examiner(s): BERGNER, ERIN FLANAGAN
• Application Number:
  US12/717,923
• Publication Number:
  US 20110159691A1
• Time in Patent Office: 1,034 Days
• Field of Search: 257/401, 257/52, 257/20, 257/734, 430/5, 430/312, 430/313, 430/314, 438/618, 438/622, 438/717, 438/734, 438/231, 438/301, 438/303, 438/592, 438/978, 438/689, 438/690, 438/692, 438/694, 438/696, 438/700, 438/702, 438/706, 438/743, 438/763, 216/40, 216/41, 361/321.4, 428/336, 716/50
• US Class Current: 438/689
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks

Abstract

A method for making a semiconductor device includes forming a first mask pattern on a device layer, forming a second mask pattern on the first mask pattern, etching the device layer not covered by the first and second mask patterns to thereby form a first trench, trimming the first mask pattern to form an intermediate mask pattern, depositing a material layer to fill the first trench, polishing the material layer to expose a top surface of the intermediate mask pattern, removing the intermediate mask pattern to form an opening, etching the device layer through the opening to thereby form a second trench.

Claims

1. A method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning, comprising:

providing a device layer;

forming a first mask pattern on the device layer;

forming a second mask pattern on the first mask pattern, wherein the second mask pattern partially covers the first mask pattern;

selectively etching the device layer not covered by the first and second mask patterns to thereby form a first trench therein;

after forming the first trench, removing the first mask pattern not covered by the second mask pattern to form an intermediate mask pattern;

depositing a mask material layer to fill the first trench and cover the intermediate mask pattern;

polishing the mask material layer to expose a top surface of the intermediate mask pattern, thereby forming a third mask pattern;

selectively removing the intermediate mask pattern to form an opening; and

etching the device layer through the opening to thereby form a second trench.

2. The method according to claim 1 wherein the device layer is a dielectric layer.

3. The method according to claim 2 wherein the dielectric layer comprises silicon oxide.

4. The method according to claim 1 wherein the device layer is a semiconductor substrate.

5. The method according to claim 4 wherein the semiconductor substrate comprises silicon substrate.

6. The method according to claim 1 wherein the device layer is a multi-layer stack structure.

7. The method according to claim 6 wherein the multi-layer stack structure comprises polysilicon-tungsten-silicon nitride stack structure.

8. The method according to claim 1 wherein the first mask pattern comprises polysilicon.

9. The method according to claim 1 wherein the second mask pattern comprises carbon.

10. The method according to claim 1 wherein the second mask pattern comprises amorphous carbon.

11. The method according to claim 1 wherein the mask material layer and the second mask pattern are composed of the same material.

12. The method according to claim 1 wherein the mask material comprises carbon or amorphous carbon.

13. The method according to claim 1 wherein the first mask pattern comprises a plurality of dense line patterns.

14. The method according to claim 13 wherein line width to space ratio (L:

S) of the plurality of dense line patterns is 1;

1.

15. The method according to claim 1 wherein an anti-reflection coating layer is provided on the second mask pattern.

16. The method according to claim 1 wherein after forming the second mask pattern on the first mask pattern, the first mask pattern and the second mask pattern together form an etching hard mask with a step structure.