Methods of forming an integrated circuit with self-aligned trench formation

• US 8,343,875 B2
• Filed: 01/10/2012
• Issued: 01/01/2013
• Est. Priority Date: 09/11/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner, Lane, Richard
• Primary Examiner(s): Lee, Calvin
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US13/347,478
• Publication Number:
  US 20120108069A1
• Time in Patent Office: 357 Days
• Field of Search: 438/424, 438/696, 257/E21.243
• US Class Current: 438/696
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set of trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.

Claims

1. A method of forming an integrated circuit, the method comprising:

forming a structure on a substrate, the structure comprising a structural material and an etch stop, the etch stop having an upper surface and a lower surface;

planarizing the structure and stopping planarizing on the etch stop;

selectively recessing the structural material such that an exposed upper surface of the structural material is approximately coplanar with the lower surface of the etch stop at the end of said selectively recessing; and

selectively removing the etch stop to leave an approximately coplanar surface including the previously exposed upper surface of the recessed structural material and an upper surface of a material exposed by removing the etch stop.

2. The method of claim 1, wherein the structural material comprises a form of silicon oxide.

3. The method of claim 1, wherein the etch stop comprises nitride.

4. The method of claim 3, wherein the etch stop comprises Si₃N₄.

5. The method of claim 3, wherein selectively removing the etch stop comprises exposing an oxide surface.

6. The method of claim 1, wherein, before selectively removing the etch stop and after planarizing, the etch stop has a thickness between about 10 Å

and 70 Å

.

7. The method of claim 1, wherein selectively recessing the structural material to be approximately coplanar with the lower surface of the etch stop comprises selectively recessing the structural material to a level within ±

20 Å

of the lower surface of the etch stop.

8. The method of claim 1, wherein the material exposed by removing the ecth stop comprises a different material than the structural material.

9. The method of claim 1, wherein the approximately coplanar surface left from selectively removing the etch stop includes substantially all materials directly surrounding the exposed upper surface of the recessed structural material in plan view.

10. The method of claim 1, further comprising:

forming a trench in the substrate; and

lining the trench with a liner layer;

wherein the etch stop and an adjacent etch stop are disposed over the substrate on opposing sides of the trench.

11. A method of forming an integrated circuit, the method comprising:

forming a structure on a substrate, the structure comprising a structural material and an etch stop adjacent the structural material, the etch stop having an upper surface at a first height above the substrate and a lower surface at a second height above the substrate;

planarizing the structure at approximately the first height;

selectively recessing the structural material to approximately the second height at the end of said selectively recessing; and

selectively removing the etch stop to expose an underlying surface, wherein the underlying surface is approximately coplanar with an exposed upper surface of the recessed structural material.

12. The method of claim 11, wherein forming the structure comprises forming the structural material comprising silicon oxide, and forming the etch stop comprising silicon nitride.

13. The method of claim 11, wherein selectively removing the etch stop exposes the underlying surface comprising an oxide.

14. The method of claim 11, wherein selectively recessing the structural material to approximately the second height comprises selectively recessing the structural material to a level within ±

20 Å

of the second height.

15. A method of forming an integrated circuit, the method comprising:

forming a structure on a substrate, the structure comprising a structural material and an etch stop, the etch stop having an upper surface and a lower surface;

forming a trench in the substrate;

lining the trench with a liner layer, wherein the etch stop and an adjacent etch stop are disposed over the substrate on opposing sides of the trench;

planarizing the structure and stopping planarizing on the etch stop;

selectively recessing the structural material such that an exposed upper surface of the structural material is approximately coplanar with the lower surface of the etch stop, wherein a portion of the liner layer protrudes above the structural material between the etch stop and the adjacent etch stop after selectively recessing the structural material; and

selectively removing the etch stop to leave an approximately coplanar surface including the exposed upper surface of the recessed structural material.

16. The method of claim 15, wherein the portion of the liner layer that protrudes above the structural material is selectively removed while selectively removing the etch stop.

17. The method of claim 15, wherein the portion of the liner layer that protrudes above the structural material comprises nitride.

18. The method of claim 17, further comprising lining the trench with at least one oxide liner layer.

19. The method of claim 18, wherein lining the trench with at least one oxide liner includes forming oxide liners on opposing sides of the liner layer.

20. The method of claim 15, wherein forming the structure comprises forming the structural material comprising silicon oxide, and forming the etch stop comprising silicon nitride.