Semiconductor device having an edge termination structure and method of manufacture thereof

• US 8,344,448 B2
• Filed: 05/21/2004
• Issued: 01/01/2013
• Est. Priority Date: 05/31/2003
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Grover, Raymond J.
• Primary Examiner(s): Lee, Eugene
• Assistant Examiner(s): ULLAH, ELIAS
• Application Number:
  US10/561,531
• Publication Number:
  US 20110291185A1
• Time in Patent Office: 3,147 Days
• Field of Search: 257/334, 257/328, 257/331, 257/496, 257/367, 257/E29.262, 257/E21.09, 438/133, 438/270, 438/268
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7817 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A semiconductor device having a semiconductor body comprising an active area and a termination structure surrounding the active area, and a method for the manufacture thereof. The invention particularly concerns a termination structure for such devices having trenched electrodes in the active area. The termination structure comprises a plurality of lateral trench-gate transistor devices connected in series and extending from the active area towards a peripheral edge of the semiconductor body. The lateral devices are arranged such that a voltage difference between the active area and the peripheral edge is distributed across the lateral devices. The termination structure is compact and features of the structure are susceptible for formation in the same process steps as features of the active area.

Claims

1. A semiconductor device having a semiconductor body comprising an active area and a termination structure surrounding the active area, the termination structure comprising a plurality of lateral trenchgate transistor devices connected in series and extending from the active area towards a peripheral edge of the semiconductor body, each lateral device comprising a trench having a gate electrode therein separated from the semiconductor body by a layer of gate insulating material, the gate electrodes of the lateral devices extending through a region of a first conductivity type, and part way through an underlying region of a second, opposite conductivity type, the first conductivity type being one of n-type or p-type and the second conductivity type being the other of n-type or p-type, with each lateral device including an electrically conductive connection arranged between its gate electrode and the first conductivity type region at the side of the lateral device closer to the active area and configured to distribute a voltage difference between the active area and the peripheral edge across the lateral devices.

2. A semiconductor device of claim 1 wherein the active area comprises devices having a region of the first conductivity type which is formed in the same process step as the first conductivity type region of the lateral devices.

3. A semiconductor device of claim 1 wherein the insulated electrodes of the active area devices are gate electrodes of the trenchgate transistor devices, and the first conductivity type region of the active area devices forms a channel-accommodating region thereof.

4. A semiconductor device of claim 1 wherein the insulated electrodes of the active area devices are trenched electrodes of Schottky rectifiers.

5. A semiconductor device of claim 1 wherein the layer of insulating material is thicker over the bottom of the trenches of the lateral devices than over at least a portion of the sidewalls of said trenches.

6. A semiconductor device of claim 1 wherein the doping level of a respective portion of the region of second conductivity type adjacent the bottom of each of the gate trenches of the lateral devices is higher than that of the remainder of the second conductivity type region.

7. A semiconductor device of claim 1 wherein the semiconductor body is rectangular in the plane of the body, and the connections are provided towards one or more corners of the body.

8. A method of forming a semiconductor device having a semiconductor body comprising an active area and a termination structure surrounding the active area, the termination structure comprising a plurality of lateral trench-gate transistor devices connected in series and extending from the active area towards a peripheral edge of the semiconductor body, each lateral device comprising a trench having a gate electrode therein separated from the semiconductor body by a layer of gate insulating material, the gate electrodes of the lateral devices extending through a region of a first conductivity type, and part way through an underlying region of a second, opposite conductivity type, the first conductivity type being one of n-type or p-type and the second conductivity type being the other of n-type or p-type, with each lateral device including an electrically conductive connection arranged between its gate electrode and the first conductivity type region at the side of the lateral device closer to the active area and configured to distribute a voltage difference between the active area and the peripheral edge across the lateral devices, the method comprising forming the trenches, gate electrodes and layers of gate insulating material of the lateral devices in the same respective process steps as trenches, insulated electrodes therein and layers of material insulating the insulated electrodes of devices in the active area.

9. A method of claim 8 comprising forming a region of the first conductivity type in devices of the active area in the same process step as the first conductivity type region of the lateral devices.

10. A semiconductor device including a semiconductor body, the semiconductor device comprising:

an active area;

a termination structure surrounding the active area;

a plurality of lateral trenchgate transistor devices in the termination structure and configured and arranged in series extending from the active area towards a peripheral edge of the semiconductor body;

a trench in each of the lateral trenchgate transistor devices;

a gate electrode, associated with each of the trenches, extending through a region of a first conductivity type, and partially through an underlying region of a second opposite conductivity type and separated from the semiconductor body by a layer of gate insulating material;

the first conductivity type being one of n-type or p-type and the second conductivity type being the other of n-type or p-type, and

an electrically conductive connection between the gate electrode of each lateral device and the first conductivity type region at the side of the lateral device closer to the active area, the electrically conductive connection being configured and arranged to distribute a voltage difference between the active area and the peripheral edge across the lateral devices.

11. A semiconductor device of claim 10 wherein the plurality of lateral trench gate transistor devices have a pitch of 2.4 microns.

12. A semiconductor device of claim 10 wherein the termination structure has a breakdown voltage greater than 35 Volts.