Stress mitigation in packaged microchips

• US 8,344,487 B2
• Filed: 06/28/2007
• Issued: 01/01/2013
• Est. Priority Date: 06/29/2006
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Zhang, Xin, Judy, Michael, Kuan, Nelson, Spooner, Timothy, Paydenkar, Chetan, Farrell, Peter, Chau, Kevin H. L.
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Laurenzi, Mark A
• Application Number:
  US11/770,369
• Publication Number:
  US 20080157298A1
• Time in Patent Office: 2,014 Days
• Field of Search: 257/676, 257/738, 257685-686, 257/774, 257/737, 257/666, 257/E23.045, 438/118, 438126-127, 438123-124
• US Class Current: 257/669
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/15747 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A packaged microchip has a lead frame with a die directly contacting at least a single, contiguous portion of the lead frame. The portion of the lead frame has a top surface forming a concavity and contacting the die. The packaged microchip also has mold material substantially encapsulating part of the top surface of the portion of the lead frame.

Claims

1. A packaged microchip comprising:

a single lead frame comprising a plurality of electrically independent leads;

a die, the die physically coupled to one of;

(a) the plurality of electrically independent leads, each of the electrically independent leads having a top surface physically coupled to the die and an outer edge, the top surface comprising a plurality of concavities between the die and the outer edge;

or

(b) a paddle, the paddle being electrically independent of the plurality of leads, the paddle having a top surface physically coupled to the die, a first outer edge and a second outer edge, the die physically coupled to the paddle between the first outer edge and the second outer edge, the top surface comprising a first plurality of concavities between the die and the first outer edge, and a second plurality of cavities between the die and the second outer edge; and

mold material substantially encapsulating part of the top surface of the portion of the lead frame,

wherein the plurality of concavities mitigate stress transmission within the lead frame.

2. The packaged microchip as defined by claim 1 further comprising an adhesive for directly contacting the die with the portion of the lead frame.

3. The packaged microchip as defined by claim 1 wherein the plurality of concavities comprise a first concavity, and a second concavity between the die and the first concavity.

4. The packaged microchip as defined by claim 1 wherein at least one of the plurality of concavities is directly beneath the die.

5. The packaged microchip as defined by claim 1 wherein the mold material substantially encapsulates the die.

6. The packaged microchip as defined by claim 1 wherein the lead frame and mold material form a post-molded package.

7. The packaged microchip as defined by claim 1 wherein the lead frame and mold material form a pre-molded package.

8. The packaged microchip as defined by claim 1 wherein the top surface is substantially planar about each concavity.

9. The packaged microchip as defined by claim 1 wherein each concavity comprises an elongated trench extending generally parallel to the die.

10. The packaged microchip as defined by claim 8 wherein at least one concavity extends through about half of the thickness of the portion of the lead frame.

11. The packaged microchip as defined by claim 1 wherein the portion of the lead frame has an edge region, the edge region being thinner than another part of the portion of the lead frame.

18. The packaged microchip as defined by claim 1 wherein at least one of the concavities had a substantially parabolic cross-section.

12. A packaged microchip comprising:

a single lead frame having a contiguous portion with an outer edge and a substantially planar top surface;

a die physically coupled to one of;

(a) the plurality of electrically independent leads, each of the electrically independent leads having a top surface physically coupled to the die and an outer edge, the top surface comprising a plurality of concavities between the die and the outer edge;

or

(b) a paddle, the paddle being electrically independent of the plurality of leads, the paddle having a top surface physically coupled to the die, a first outer edge and a second outer edge, the die physically coupled to the paddle between the first outer edge and the second outer edge, the top surface comprising a first plurality of concavities between the die and the first outer edge, and a second plurality of cavities between the die and the second outer edge; and

mold material substantially encapsulating part of the top surface of the portion of the lead frame,

wherein the plurality of concavities mitigate stress transmission within the lead frame.

13. The packaged microchip as defined by claim 12 wherein each concavity comprises an elongated trench extending generally parallel to the die.

14. The packaged microchip as defined by claim 13 wherein at least one trench extends through about half of the thickness of the portion of the lead frame.

15. The packaged microchip as defined by claim 12 wherein at least one concavity is positioned beneath the die.

16. A packaged microchip comprising:

a lead frame having a contiguous, substantially planar portion with a top surface;

a die physically coupled to one of;

(a) the plurality of electrically independent leads, each of the electrically independent leads having a top surface physically coupled to the die and an outer edge, the top surface comprising a plurality of concavities between the die and the outer edge;

or

(b) a paddle, the paddle being electrically independent of the plurality of leads, the paddle having a top surface physically coupled to the die, a first outer edge and a second outer edge, the die physically coupled to the paddle between the first outer edge and the second outer edge, the top surface comprising a first plurality of concavities between the die and the first outer edge, and a second plurality of cavities between the die and the second outer edge; and

mold material substantially encapsulating part of the top surface of the portion of the lead frame to form a pre-molded package,

the top surface of the substantially planar portion of the lead frame comprising means for mitigating stress produced by coefficient of thermal expansion differentials of the lead frame and die.

17. The packaged microchip as defined by claim 16 wherein the mitigating means comprises a concavity within the planar portion of the lead frame.