Barrier for through-silicon via

• US 8,344,513 B2
• Filed: 12/04/2009
• Issued: 01/01/2013
• Est. Priority Date: 03/23/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chiou, Wen-Chih, Wu, Weng-Jin
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US12/631,172
• Publication Number:
  US 20100237502A1
• Time in Patent Office: 1,124 Days
• Field of Search: 257/741, 257/751, 257/763, 257/773, 257/E21.171, 257/E21.175, 257/E21.575, 257/E21.584, 438/618, 438/627, 438/641, 438/656
• US Class Current: 257/773
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01025 Manganese [Mn]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 being a resistor

Abstract

A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of the opening. A seed layer is formed over the barrier layer, and the TSV opening is filled with a conductive filler. Another embodiment includes a barrier layer formed using atomic layer deposition.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having an opening;

a liner formed along sidewalls of the opening, the liner comprising a dielectric material;

a barrier layer overlying the liner along the sidewalls of the opening, the barrier layer comprising fluorine, wherein the content of fluorine is no more than about 15% of the barrier layer;

a seed layer overlying the barrier layer along the sidewalls of the opening; and

a conductive material formed on the seed layer and filling the opening, the conductive material being part of a through substrate via.

2. The semiconductor device of claim 1, further comprising a first adhesion layer between the barrier layer and the seed layer.

3. The semiconductor device of claim 2, wherein the first adhesion layer comprises Ta or TaN.

4. The semiconductor device of claim 1, wherein the seed layer comprises manganese or aluminum.

5. The semiconductor device of claim 1, wherein the barrier layer comprises tantalum nitride, tantalum, titanium, titanium nitride or combinations thereof.

6. The semiconductor device of claim 1, wherein the liner comprises an oxide layer or a silicon nitride layer.

7. The semiconductor device of claim 1, further comprising an adhesion layer between the barrier layer and the liner.

8. The semiconductor device of claim 7, wherein the adhesion layer comprises Ta or TaN.

9. The semiconductor device of claim 1, wherein the seed layer and the conductive material comprise copper.

10. The semiconductor device of claim 1, wherein the content of carbon is no more than about 15% of the barrier layer.

11. A method of manufacturing a semiconductor device comprising:

providing a substrate with an opening located therein;

forming a dielectric liner along sidewalls of the opening;

forming a barrier layer over the liner and along the sidewalls and a bottom of the opening using an atomic layer deposition process and introducing an alloying material into the barrier layer, the alloying material comprises fluorine, with a content of not more than about 15% of the alloying material;

forming a seed layer overlying the barrier layer;

forming a conductive material on the seed layer, filling the opening; and

removing a portion of the substrate to expose the conductive material.

12. The method of claim 11, further comprising forming a first adhesion layer on the barrier layer prior to the forming a seed layer.

13. The method of claim 11, wherein the seed layer comprises manganese or aluminum.

14. The method of claim 11, further comprising forming an adhesion layer along the sidewalls and bottom of the opening prior to the forming a barrier layer.

15. The method of claim 11, wherein the barrier layer comprises tantalum nitride, tantalum, titanium, titanium nitride or combinations thereof.

16. The method of claim 11, wherein the seed layer and the conductive material comprise copper.